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flow: designs: ihp-sg13g2: Update Designs
Update all ihp-sg13g2 designs to match the latest PDK files. Additionally, lower frequency for spi and gdc design to meet worst-case latency. Signed-off-by: Daniel Schultz <[email protected]>
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11 files changed

+42
-119
lines changed

11 files changed

+42
-119
lines changed

‎flow/designs/ihp-sg13g2/aes/rules-base.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -140,4 +140,4 @@
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"value": 1054989,
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"compare": "<="
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}
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}
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}

‎flow/designs/ihp-sg13g2/gcd/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design gcd
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 2.6
5+
set clk_period 2.8
66
set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]

‎flow/designs/ihp-sg13g2/gcd/rules-base.json‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -30,19 +30,19 @@
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
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"value": 5458.22361,
33+
"value": 6828.9632,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 6195,
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"value": 7382,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 494,
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"value": 614,
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"compare": "<="
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},
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"detailedplace__design__violations": {
@@ -94,7 +94,7 @@
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 12621,
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"value": 15132,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -142,7 +142,7 @@
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 26057,
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"value": 7693,
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"compare": "<="
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}
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}
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}

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,14 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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99
export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz
1010

11-
export DIE_AREA = 0.0 0.0 1050.0 1050.0
11+
export DIE_AREA = 0.0 0.0 1050.24 1050.84
1212
export CORE_AREA = 351.36 351.54 699.84 699.3
1313

1414
export MAX_ROUTING_LAYER = TopMetal2
1515

1616
export TNS_END_PERCENT = 100
1717
export PLACE_DENSITY = 0.75
18-
18+
export MACRO_PLACE_HALO = 20 20
1919
export CORNERS = slow fast
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export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,9 @@ create_clock [get_pins sg13g2_IOPad_io_clock/p2c] -name clk_core -period 20.0 -w
1010
set_clock_uncertainty 0.15 [get_clocks clk_core]
1111
set_clock_transition 0.25 [get_clocks clk_core]
1212

13+
set input_delay_value_clk_core 4.0
14+
set output_delay_value_clk_core 4.0
15+
1316
set clock_ports [get_ports {
1417
io_clock_PAD
1518
}]
@@ -26,16 +29,16 @@ set clk_core_inout_16mA_ports [get_ports {
2629
io_gpio_7_PAD
2730
}]
2831
set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports
29-
set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports
30-
set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports
32+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_inout_16mA_ports
33+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_inout_16mA_ports
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3235
set clk_core_inout_4mA_ports [get_ports {
3336
io_i2c_scl_PAD
3437
io_i2c_sda_PAD
3538
}]
3639
set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports
37-
set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports
38-
set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports
40+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_inout_4mA_ports
41+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_inout_4mA_ports
3942

4043
set clk_core_input_ports [get_ports {
4144
io_reset_PAD
@@ -44,13 +47,13 @@ set clk_core_input_ports [get_ports {
4447
io_address_2_PAD
4548
}]
4649
set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports
47-
set_input_delay 8 -clock clk_core $clk_core_input_ports
50+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_input_ports
4851

4952
set clk_core_output_4mA_ports [get_ports {
5053
io_i2c_interrupt_PAD
5154
}]
5255
set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports
53-
set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports
56+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_output_4mA_ports
5457

5558
set_load -pin_load 5 [all_inputs]
5659
set_load -pin_load 5 [all_outputs]

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,19 +97,19 @@
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 965,
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"value": 953,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 84,
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"value": 83,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 84,
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"value": 83,
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"compare": "<="
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},
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"cts__timing__setup__ws": {
@@ -197,7 +197,7 @@
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 135675,
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"value": 42034,
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"compare": "<="
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}
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}

‎flow/designs/ihp-sg13g2/ibex/rules-base.json‎

Lines changed: 2 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,4 @@
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{
2-
"detailedroute__flow__warnings__count:DRT-0349": {
3-
"value": 10,
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"compare": "<=",
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"level": "warning"
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},
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"finish__flow__warnings__count:GUI-0076": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"floorplan__flow__warnings__count:EST-0027": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"floorplan__flow__warnings__count:IFP-0028": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"globalroute__flow__warnings__count:DRT-0349": {
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"value": 10,
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"compare": "<=",
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
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"value": 305820.24,
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"compare": "<="
@@ -89,7 +64,7 @@
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
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"value": 999955,
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"value": 989089,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -137,7 +112,7 @@
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 645302,
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"value": 314511,
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"compare": "<="
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}
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}

‎flow/designs/ihp-sg13g2/jpeg/rules-base.json‎

Lines changed: 4 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,4 @@
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{
2-
"detailedroute__flow__warnings__count:DRT-0349": {
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"value": 10,
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"compare": "<=",
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"level": "warning"
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},
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"finish__flow__warnings__count:GUI-0076": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"floorplan__flow__warnings__count:IFP-0028": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"globalroute__flow__warnings__count:DRT-0349": {
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"value": 10,
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"compare": "<=",
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
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"value": 1499147.11,
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"compare": "<="
@@ -48,7 +28,7 @@
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"compare": "<="
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},
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"cts__timing__setup__ws": {
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"value": -0.4,
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"value": 0.0,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
@@ -68,7 +48,7 @@
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
71-
"value": -0.4,
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"value": -0.0182,
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"compare": ">="
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},
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"globalroute__timing__setup__tns": {
@@ -96,7 +76,7 @@
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
99-
"value": 166,
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"value": 132,
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"compare": "<="
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},
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"detailedroute__timing__setup__ws": {
@@ -132,7 +112,7 @@
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 3104666,
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"value": 1059270,
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"compare": "<="
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}
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}

‎flow/designs/ihp-sg13g2/riscv32i/rules-base.json‎

Lines changed: 4 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,4 @@
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{
2-
"detailedroute__flow__warnings__count:DRT-0349": {
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"value": 10,
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"compare": "<=",
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"level": "warning"
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},
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"finish__flow__warnings__count:GUI-0076": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"floorplan__flow__warnings__count:EST-0027": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"floorplan__flow__warnings__count:IFP-0028": {
18-
"value": 1,
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"compare": "<=",
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"level": "warning"
21-
},
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"flow__warnings__count:FIN-0010": {
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"value": 12,
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"compare": "<=",
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"level": "warning"
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},
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"globalroute__flow__warnings__count:DRT-0349": {
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"value": 10,
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"compare": "<=",
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"level": "warning"
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},
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"globalroute__flow__warnings__count:RSZ-0062": {
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"value": 1,
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"compare": "<=",
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
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"value": 151466.57,
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"compare": "<="
@@ -63,7 +28,7 @@
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"compare": "<="
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},
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"cts__timing__setup__ws": {
66-
"value": -0.3,
31+
"value": -0.0277,
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"compare": ">="
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},
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"cts__timing__setup__tns": {
@@ -83,11 +48,11 @@
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"compare": "<="
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},
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"globalroute__timing__setup__ws": {
86-
"value": -0.331,
51+
"value": -0.1853,
8752
"compare": ">="
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},
8954
"globalroute__timing__setup__tns": {
90-
"value": -1.23,
55+
"value": 0.0,
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"compare": ">="
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},
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"globalroute__timing__hold__ws": {
@@ -147,7 +112,7 @@
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 411968,
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"value": 168818,
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"compare": "<="
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}
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}

‎flow/designs/ihp-sg13g2/spi/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design spi
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 0.9
5+
set clk_period 1.0
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

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