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config_mpl2 for ca53 and bp_single
Signed-off-by: Ravi Varadarajan <[email protected]>
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‎flow/designs/gf12/bp_single/config_mpl2.mk‎

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export DESIGN_NICKNAME = bp_single
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export DESIGN_NAME = bsg_chip
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export PLATFORM = gf12
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = True
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#
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
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export RTLMP_MIN_INST = 10000
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export RTLMP_MAX_MACRO = 24
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export RTLMP_MIN_MACRO = 4
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#
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export RTLMP_FENCE_LX ?= 900
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export RTLMP_FENCE_LY ?= 1300
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export RTLMP_FENCE_UX ?= 2350
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export RTLMP_FENCE_UY ?= 2500
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#netlist
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export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yosys/bp_single_hier_yosys_netlist.v \
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$(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v
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export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yosys/bp_single_hier_yosys_netlist.v
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export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/bsg_chip.elab.v.sdc
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export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
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$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
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$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
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$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
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$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
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$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
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$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef
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export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
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export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib
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export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
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$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \
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$(PLATFORM_DIR)/gds/gf12_1rw_d256_w48_m2.gds2 \
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$(PLATFORM_DIR)/gds/gf12_1rw_d512_w64_m2_byte.gds2 \
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$(PLATFORM_DIR)/gds/gf12_1rw_d64_w124_m2_bit.gds2 \
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$(PLATFORM_DIR)/gds/gf12_1rw_d64_w62_m2_bit.gds2 \
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$(PLATFORM_DIR)/gds/IN12LP_GPIO18_13M9S30P.gds \
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$(PLATFORM_DIR)/gds/GoLd_LN14_CDMM_32xxx.gds.gz
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export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds
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export FOOTPRINT ?= $(PLATFORM_DIR)/bp/bsg_bp_single.package.strategy
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export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap
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export ABC_CLOCK_PERIOD_IN_PS = 1250
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export PLACE_DENSITY = 0.55
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export TNS_END_PERCENT = 0
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export HAS_IO_CONSTRAINTS = 1
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export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
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export PDN_TCL ?= $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
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export MACRO_PLACE_HALO = 7 7
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export MACRO_PLACE_CHANNEL = 14 14
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export DESIGN_TYPE = CHIP
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# enable slack margin for setup and hold fix after CTS
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export SETUP_SLACK_MARGIN ?= 100

‎flow/designs/gf12/ca53/config_mpl2.mk‎

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export DESIGN_NAME = ca53_cpu
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export PLATFORM = gf12
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export FLOW_VARIANT ?= mpl2
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = True
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export VERILOG_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
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export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
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export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc
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export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sc9mcpp84_12lp_base_lvt_c14.lef
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export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sc9mcpp84_12lp_base_lvt_c14_tt_nominal_max_0p80v_25c.lib
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export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sc9mcpp84_12lp_base_lvt_c14.gds2
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export WRAP_LEFS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.lef \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.lef
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export WRAP_LIBS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib
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export ADDITIONAL_GDS += $(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.gds2 \
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$(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.gds2
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# These values must be multiples of placement site
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export DIE_AREA = 0 0 1400 1400
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export CORE_AREA = 10 10 1390 1390
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export HAS_IO_CONSTRAINTS = 1
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export PLACE_PINS_ARGS = -exclude left:0-600 -exclude left:1350-1400 -exclude right:* -exclude top:* -exclude bottom:*
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export MACRO_PLACE_HALO = 7 7
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export MACRO_PLACE_CHANNEL = 14 14
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export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG))/wrappers.tcl
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export PLACE_DENSITY_LB_ADDON = 0.05
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#export MAX_ROUTING_LAYER = H2
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export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG))/fastroute.tcl
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#
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ifneq ($(USE_FILL),)
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export DESIGN_TYPE = CELL
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else
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export DESIGN_TYPE = CELL_NODEN
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endif

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