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flow: designs: ihp-sg13g2: Update Designs
Update all ihp-sg13g2 designs to match the latest PDK files. Additionally, lower frequency for spi and gdc design to meet worst-case latency. Signed-off-by: Daniel Schultz <[email protected]>
1 parent 9278cc8 commit 310f0ea

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10 files changed

+45
-42
lines changed

10 files changed

+45
-42
lines changed

‎flow/designs/ihp-sg13g2/gcd/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design gcd
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 2.6
5+
set clk_period 2.8
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/ihp-sg13g2/gcd/rules-base.json‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -30,19 +30,19 @@
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"level": "warning"
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},
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"synth__design__instance__area__stdcell": {
33-
"value": 5458.22361,
33+
"value": 6828.9632,
3434
"compare": "<="
3535
},
3636
"constraints__clocks__count": {
3737
"value": 1,
3838
"compare": "=="
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},
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"placeopt__design__instance__area": {
41-
"value": 6195,
41+
"value": 7382,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
45-
"value": 494,
45+
"value": 614,
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"compare": "<="
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},
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"detailedplace__design__violations": {
@@ -94,7 +94,7 @@
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
97-
"value": 12621,
97+
"value": 15132,
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"compare": "<="
9999
},
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"detailedroute__route__drc_errors": {
@@ -142,7 +142,7 @@
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"compare": ">="
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},
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"finish__design__instance__area": {
145-
"value": 26057,
145+
"value": 7693,
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"compare": "<="
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}
148-
}
148+
}

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,14 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

99
export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz
1010

11-
export DIE_AREA = 0.0 0.0 1050.0 1050.0
11+
export DIE_AREA = 0.0 0.0 1050.24 1050.84
1212
export CORE_AREA = 351.36 351.54 699.84 699.3
1313

1414
export MAX_ROUTING_LAYER = TopMetal2
1515

1616
export TNS_END_PERCENT = 100
1717
export PLACE_DENSITY = 0.75
18-
18+
export MACRO_PLACE_HALO = 20 20
1919
export CORNERS = slow fast
2020

2121
export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,9 @@ create_clock [get_pins sg13g2_IOPad_io_clock/p2c] -name clk_core -period 20.0 -w
1010
set_clock_uncertainty 0.15 [get_clocks clk_core]
1111
set_clock_transition 0.25 [get_clocks clk_core]
1212

13+
set input_delay_value_clk_core 4.0
14+
set output_delay_value_clk_core 4.0
15+
1316
set clock_ports [get_ports {
1417
io_clock_PAD
1518
}]
@@ -26,16 +29,16 @@ set clk_core_inout_16mA_ports [get_ports {
2629
io_gpio_7_PAD
2730
}]
2831
set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports
29-
set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports
30-
set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports
32+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_inout_16mA_ports
33+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_inout_16mA_ports
3134

3235
set clk_core_inout_4mA_ports [get_ports {
3336
io_i2c_scl_PAD
3437
io_i2c_sda_PAD
3538
}]
3639
set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports
37-
set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports
38-
set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports
40+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_inout_4mA_ports
41+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_inout_4mA_ports
3942

4043
set clk_core_input_ports [get_ports {
4144
io_reset_PAD
@@ -44,13 +47,13 @@ set clk_core_input_ports [get_ports {
4447
io_address_2_PAD
4548
}]
4649
set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports
47-
set_input_delay 8 -clock clk_core $clk_core_input_ports
50+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_input_ports
4851

4952
set clk_core_output_4mA_ports [get_ports {
5053
io_i2c_interrupt_PAD
5154
}]
5255
set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports
53-
set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports
56+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_output_4mA_ports
5457

5558
set_load -pin_load 5 [all_inputs]
5659
set_load -pin_load 5 [all_outputs]

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,19 +97,19 @@
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"compare": "<="
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},
9999
"placeopt__design__instance__count__stdcell": {
100-
"value": 965,
100+
"value": 953,
101101
"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
107107
"cts__design__instance__count__setup_buffer": {
108-
"value": 84,
108+
"value": 83,
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"compare": "<="
110110
},
111111
"cts__design__instance__count__hold_buffer": {
112-
"value": 84,
112+
"value": 83,
113113
"compare": "<="
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},
115115
"cts__timing__setup__ws": {
@@ -197,7 +197,7 @@
197197
"compare": ">="
198198
},
199199
"finish__design__instance__area": {
200-
"value": 135675,
200+
"value": 42034,
201201
"compare": "<="
202202
}
203203
}

‎flow/designs/ihp-sg13g2/ibex/rules-base.json‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -89,11 +89,11 @@
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"compare": ">="
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},
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"detailedroute__route__wirelength": {
92-
"value": 999955,
92+
"value": 993383,
9393
"compare": "<="
9494
},
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"detailedroute__route__drc_errors": {
96-
"value": 0,
96+
"value": 4,
9797
"compare": "<="
9898
},
9999
"detailedroute__antenna__violating__nets": {
@@ -137,7 +137,7 @@
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"compare": ">="
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},
139139
"finish__design__instance__area": {
140-
"value": 645302,
140+
"value": 314511,
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"compare": "<="
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}
143143
}

‎flow/designs/ihp-sg13g2/jpeg/rules-base.json‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@
4848
"compare": "<="
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},
5050
"cts__timing__setup__ws": {
51-
"value": -0.4,
51+
"value": 0.0,
5252
"compare": ">="
5353
},
5454
"cts__timing__setup__tns": {
@@ -68,7 +68,7 @@
6868
"compare": "<="
6969
},
7070
"globalroute__timing__setup__ws": {
71-
"value": -0.4,
71+
"value": -0.0182,
7272
"compare": ">="
7373
},
7474
"globalroute__timing__setup__tns": {
@@ -96,7 +96,7 @@
9696
"compare": "<="
9797
},
9898
"detailedroute__antenna_diodes_count": {
99-
"value": 166,
99+
"value": 138,
100100
"compare": "<="
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},
102102
"detailedroute__timing__setup__ws": {
@@ -132,7 +132,7 @@
132132
"compare": ">="
133133
},
134134
"finish__design__instance__area": {
135-
"value": 3104666,
135+
"value": 1059373,
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"compare": "<="
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}
138-
}
138+
}

‎flow/designs/ihp-sg13g2/riscv32i/rules-base.json‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@
6363
"compare": "<="
6464
},
6565
"cts__timing__setup__ws": {
66-
"value": -0.3,
66+
"value": -0.0277,
6767
"compare": ">="
6868
},
6969
"cts__timing__setup__tns": {
@@ -83,11 +83,11 @@
8383
"compare": "<="
8484
},
8585
"globalroute__timing__setup__ws": {
86-
"value": -0.331,
86+
"value": -0.1853,
8787
"compare": ">="
8888
},
8989
"globalroute__timing__setup__tns": {
90-
"value": -1.23,
90+
"value": 0.0,
9191
"compare": ">="
9292
},
9393
"globalroute__timing__hold__ws": {
@@ -103,7 +103,7 @@
103103
"compare": "<="
104104
},
105105
"detailedroute__route__drc_errors": {
106-
"value": 0,
106+
"value": 4,
107107
"compare": "<="
108108
},
109109
"detailedroute__antenna__violating__nets": {
@@ -147,7 +147,7 @@
147147
"compare": ">="
148148
},
149149
"finish__design__instance__area": {
150-
"value": 411968,
150+
"value": 169220,
151151
"compare": "<="
152152
}
153-
}
153+
}

‎flow/designs/ihp-sg13g2/spi/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design spi
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 0.9
5+
set clk_period 1.0
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/ihp-sg13g2/spi/rules-base.json‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -53,11 +53,11 @@
5353
"compare": "=="
5454
},
5555
"placeopt__design__instance__area": {
56-
"value": 3005,
56+
"value": 2662,
5757
"compare": "<="
5858
},
5959
"placeopt__design__instance__count__stdcell": {
60-
"value": 181,
60+
"value": 179,
6161
"compare": "<="
6262
},
6363
"detailedplace__design__violations": {
@@ -73,7 +73,7 @@
7373
"compare": "<="
7474
},
7575
"cts__timing__setup__ws": {
76-
"value": -0.045,
76+
"value": 0.0,
7777
"compare": ">="
7878
},
7979
"cts__timing__setup__tns": {
@@ -93,11 +93,11 @@
9393
"compare": "<="
9494
},
9595
"globalroute__timing__setup__ws": {
96-
"value": -0.056,
96+
"value": -0.0426,
9797
"compare": ">="
9898
},
9999
"globalroute__timing__setup__tns": {
100-
"value": -0.241,
100+
"value": 0.0,
101101
"compare": ">="
102102
},
103103
"globalroute__timing__hold__ws": {
@@ -109,7 +109,7 @@
109109
"compare": ">="
110110
},
111111
"detailedroute__route__wirelength": {
112-
"value": 4456,
112+
"value": 3686,
113113
"compare": "<="
114114
},
115115
"detailedroute__route__drc_errors": {
@@ -157,7 +157,7 @@
157157
"compare": ">="
158158
},
159159
"finish__design__instance__area": {
160-
"value": 11935,
160+
"value": 2767,
161161
"compare": "<="
162162
}
163-
}
163+
}

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