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1 parent b7bd3a1 commit 3137559Copy full SHA for 3137559
flow/Makefile
@@ -454,6 +454,8 @@ else ifneq ($(FOOTPRINT_TCL),)
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IS_CHIP = 1
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endif
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+UNSET_AND_MAKE = @bash -c 'for var in $(ISSUE_VARIABLES_NAMES); do unset $$var; done; echo $(MAKE) DESIGN_CONFIG=$(DESIGN_CONFIG) $$@; $(MAKE) DESIGN_CONFIG=$(DESIGN_CONFIG) $$@' --
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+
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# STEP 1: Translate verilog to odb
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#-------------------------------------------------------------------------------
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$(RESULTS_DIR)/2_1_floorplan.odb: $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL)
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