ADDITIONAL_GDS_FILES is a mis-spelling og ADDITIONAL_GDS

ADDITIONAL_LEFS/LIBS sets the precedence

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/sky130hd/chameleon/config.mk

@@ -34,7 +34,7 @@ export CORE_AREA  = 20 20 2900 3500
 
 export chameleon_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)
 
-export ADDITIONAL_GDS_FILES  = $(chameleon_DIR)/gds/apb_sys_0.gds.gz \
+export ADDITIONAL_GDS  = $(chameleon_DIR)/gds/apb_sys_0.gds.gz \
                                $(chameleon_DIR)/gds/DMC_32x16HC.gds.gz \
                                $(chameleon_DIR)/gds/DFFRAM_4K.gds.gz \
                                $(chameleon_DIR)/gds/ibex_wrapper.gds.gz

flow/designs/sky130hd/microwatt/config.mk

@@ -17,7 +17,7 @@ export ABC_CLOCK_PERIOD_IN_PS = 25000
 
 export microwatt_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)
 
-export ADDITIONAL_GDS_FILES  = $(wildcard $(microwatt_DIR)/gds/*.gds.gz)
+export ADDITIONAL_GDS  = $(wildcard $(microwatt_DIR)/gds/*.gds.gz)
 
 export ADDITIONAL_LEFS  = $(wildcard $(microwatt_DIR)/lef/*.lef)
 

flow/platforms/sky130hd/config.mk

@@ -10,7 +10,7 @@ export SC_LEF = $(PLATFORM_DIR)/lef/sky130_fd_sc_hd_merged.lef
 export LIB_FILES = $(PLATFORM_DIR)/lib/sky130_fd_sc_hd__tt_025C_1v80.lib \
                      $(ADDITIONAL_LIBS)
 export GDS_FILES = $(wildcard $(PLATFORM_DIR)/gds/*.gds) \
-                     $(ADDITIONAL_GDS_FILES)
+                     $(ADDITIONAL_GDS)
 
 # Dont use cells to ease congestion
 # Specify at least one filler cell if none

flow/platforms/sky130hs/config.mk

@@ -10,7 +10,7 @@ export SC_LEF = $(PLATFORM_DIR)/lef/sky130_fd_sc_hs_merged.lef
 export LIB_FILES = $(PLATFORM_DIR)/lib/sky130_fd_sc_hs__tt_025C_1v80.lib \
                      $(ADDITIONAL_LIBS)
 export GDS_FILES = $(wildcard $(PLATFORM_DIR)/gds/*.gds) \
-                     $(ADDITIONAL_GDS_FILES)
+                     $(ADDITIONAL_GDS)
 
 # Dont use cells to ease congestion
 # Specify at least one filler cell if none

flow/scripts/sc/util/parse_target_config.py

@@ -72,7 +72,7 @@ def parse(chip, platform):
 
     # Convert source files to absolute paths b/c sc commands run in a different build dir.
     abs_sources = ['VERILOG_INCLUDE_DIRS', 'ADDITIONAL_LEFS', 'ADDITIONAL_LIBS',
-                   'LIB_FILES', 'ADDITIONAL_GDS_FILES', 'MACRO_PLACEMENT']
+                   'LIB_FILES', 'ADDITIONAL_GDS', 'MACRO_PLACEMENT']
     for skey in abs_sources:
         if skey in config.keys():
             src_list = [os.path.abspath(vf) for vf in config[skey].split()]