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povikpovik
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Move Ibex SV sources to src/ibex_sv/
Signed-off-by: Martin Povišer <[email protected]>
1 parent 6b9b689 commit 3476020

34 files changed

+24
-24
lines changed

‎flow/designs/asap7/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,11 @@ export PLATFORM = asap7
33
export DESIGN_NICKNAME = ibex
44
export DESIGN_NAME = ibex_core
55

6-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
7+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
88

99
export VERILOG_INCLUDE_DIRS = \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
10+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1111

1212
export SYNTH_USE_SLANG = 1
1313

‎flow/designs/gf12/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
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export PLATFORM = gf12
44

5-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
6+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
77

88
export VERILOG_INCLUDE_DIRS = \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
9+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1010

1111
export SYNTH_USE_SLANG = 1
1212

‎flow/designs/gf180/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = gf180
44

5-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
6+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
77

88
export VERILOG_INCLUDE_DIRS = \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
9+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1010

1111
export SYNTH_USE_SLANG = 1
1212

‎flow/designs/ihp-sg13g2/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = ihp-sg13g2
44

5-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
6+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
77

88
export VERILOG_INCLUDE_DIRS = \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
9+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1010

1111
export SYNTH_USE_SLANG = 1
1212

‎flow/designs/intel16/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@ export DESIGN_NICKNAME = ibex
55
export DESIGN_NAME = ibex_core
66
export PLATFORM = intel16
77

8-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
8+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
9+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
1010

1111
export VERILOG_INCLUDE_DIRS = \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
12+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1313

1414
export SYNTH_USE_SLANG = 1
1515

‎flow/designs/nangate45/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = nangate45
44

5-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
6+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
77

88
export VERILOG_INCLUDE_DIRS = \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
9+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1010

1111
export SYNTH_USE_SLANG = 1
1212

‎flow/designs/sky130hd/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = sky130hd
44

5-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
6+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
77

88
export VERILOG_INCLUDE_DIRS = \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
9+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1010

1111
export SYNTH_USE_SLANG = 1
1212

‎flow/designs/sky130hs/ibex/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = sky130hs
44

5-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
6+
$(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
77

88
export VERILOG_INCLUDE_DIRS = \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
9+
$(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
1010

1111
export SYNTH_USE_SLANG = 1
1212

flow/designs/src/ibex/BUILD.bazel renamed to flow/designs/src/ibex_sv/BUILD.bazel

File renamed without changes.

flow/designs/src/ibex/LICENSE renamed to flow/designs/src/ibex_sv/LICENSE

File renamed without changes.

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