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Merge branch 'master' into gate_cloning_on_by_default
Signed-off-by: Harsh Vardhan <[email protected]>
2 parents 3ea267e + 921dd1f commit 394f971

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‎docs/user/FlowVariables.md‎

Lines changed: 47 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -35,14 +35,12 @@ public platforms supported by the OpenROAD flow.
3535
Note:
3636
- = indicates default definition assigned by the tool
3737
- ?= indicates that the variable value may be reassigned with design `config.mk`
38-
- N/A indicates that the variable/files is not supported currently.
3938

4039

4140
| **Configuration Variable** | **sky130hd** | **sky130hs** | **nangate45** | **asap7** | **gf180** |
4241
|--------------------------------------|--------------|--------------|---------------|-----------|-----------|
4342
| Library Setup | | | | | |
4443
| `PROCESS` | = | = | = | = | = |
45-
| `CORNER` | N/A | N/A | N/A | ?= | ?= |
4644
| `TECH_LEF` | = | = | = | = | = |
4745
| `SC_LEF` | = | = | = | = | = |
4846
| `LIB_FILES` | = | = | = | = | = |
@@ -62,8 +60,6 @@ Note:
6260
| `PLACE_SITE` | = | = | = | = | = |
6361
| `MAKE_TRACKS` | = | = | = | = | = |
6462
| `TAPCELL_TCL` | = | = | = | = | = |
65-
| `MACRO_HALO_X` | NA | NA | NA | ?= | NA |
66-
| `MACRO_HALO_Y` | NA | NA | NA | ?= | NA |
6763
| `MACRO_PLACE_HALO` | ?= | ?= | ?= | ?= | ?= |
6864
| `MACRO_PLACE_CHANNEL` | ?= | ?= | ?= | ?= | ?= |
6965
| `PDN_TCL` | ?= | ?= | ?= | ?= | ?= |
@@ -82,12 +78,11 @@ Note:
8278
| `SKIP_PIN_SWAP` | ?= | ?= | ?= | ?= | ?= |
8379
| `TNS_END_PERCENT` | ?= | ?= | | ?= | ?= |
8480
| Routing | | | | | |
85-
| `FASTROUTE_TCL` | ?= | ?= | ?= | N/A | N/A |
86-
| `FILL_CONFIG` | = | = | N/A | N/A | N/A |
8781
| `KLAYOUT_TECH_FILE` | = | = | = | = | = |
8882
| `MAX_ROUTING_LAYER` | = | = | = | = | ?= |
8983
| `MIN_ROUTING_LAYER` | = | = | = | = | ?= |
9084
| `RCX_RULES` | = | = | = | = | = |
85+
| `RECOVER_POWER` | ?= | ?= | ?= | ?= | ?= |
9186

9287

9388
### Library Setup
@@ -119,6 +114,7 @@ Note:
119114
| `ABC_CLOCK_PERIOD_IN_PS` | Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`. |
120115
| `ABC_DRIVER_CELL` | Default driver cell used during ABC synthesis. |
121116
| `ABC_LOAD_IN_FF` | During synthesis set_load value used. |
117+
| `MAX_UNGROUP_SIZE` | For hierarchical synthesis, we ungroup modules of size given by this variable. |
122118

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124120
### Floorplan
@@ -163,7 +159,7 @@ Note:
163159
| `SLEW_MARGIN` | Specifies a slew margin when fixing max slew violations. This option allow you to overfix. |
164160

165161

166-
### Clock Tree Synthesis(CTS)
162+
### Clock Tree Synthesis (CTS)
167163

168164

169165
| Variable | Description |
@@ -172,7 +168,7 @@ Note:
172168
| `FILL_CELLS` | Fill cells are used to fill empty sites. |
173169
| `HOLD_SLACK_MARGIN` | Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. |
174170
| `SETUP_SLACK_MARGIN` | Specifies a time margin for the slack when fixing setup violations. |
175-
| `SKIP_GATE_CLONING` | Do not use gate cloning transform to fix timing violations when appropriate (default: use cloning) |
171+
| `SKIP_GATE_CLONING` | Do not use gate cloning transform to fix timing violations (default: use gate cloning) |
176172
| `SKIP_PIN_SWAP` | Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) |
177173
| `TNS_END_PERCENT` | Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed |
178174

@@ -181,11 +177,12 @@ Note:
181177

182178

183179
| Variable | Description |
184-
|-----------------------|-------------------------------------------------------------------------|
185-
| `MIN_ROUTING_LAYER` | The lowest metal layer name to be used in routing. |
186-
| `MAX_ROUTING_LAYER` | The highest metal layer name to be used in routing. |
187-
| `DETAILED_ROUTE_ARGS` | Add additional arguments for debugging purpose during detail route. |
188-
| `MACRO_EXTENSION` | Sets the number of GCells added to the blockages boundaries from macros.|
180+
|-----------------------|---------------------------------------------------------------------------------------------------|
181+
| `MIN_ROUTING_LAYER` | The lowest metal layer name to be used in routing. |
182+
| `MAX_ROUTING_LAYER` | The highest metal layer name to be used in routing. |
183+
| `DETAILED_ROUTE_ARGS` | Add additional arguments for debugging purpose during detail route. |
184+
| `MACRO_EXTENSION` | Sets the number of GCells added to the blockages boundaries from macros. |
185+
| `RECOVER_POWER` | Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100]. |
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191188
### Extraction
@@ -236,12 +233,18 @@ configuration file.
236233
| `ADDITIONAL_LIBS` | Hardened macro library files listed here. |
237234
| `ADDITIONAL_GDS` | Hardened macro GDS files listed here. |
238235
| `VERILOG_INCLUDE_DIRS` | Specifies the include directories for the Verilog input files. |
239-
| `CORNER` | PVT corner library selection. |
236+
| `CORNER` | PVT corner library selection. Only available for ASAP7 and GF180 PDK. |
240237
| `DESIGN_NICKNAME` | DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a difference design. |
241238
| `ABC_AREA` | Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED. |
242239
| `PWR_NETS_VOLTAGES` | Used for IR Drop calculation. |
243240
| `GND_NETS_VOLTAGES` | Used for IR Drop calculation. |
244-
241+
| `BLOCKS` | Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by [Makefile](../main/flow/Makefile) |
242+
| `CDL_FILES` | Insert additional Circuit Description Language (`.cdl`) netlist files. |
243+
| `DFF_LIB_FILES` | Technology mapping liberty files for flip-flops. |
244+
| `DONT_USE_LIBS` | Set liberty files as `dont_use`. |
245+
| `PRESERVE_CELLS` | Mark modules to keep from getting removed in flattening. |
246+
| `SYNTH_ARGS` | Optional synthesis variables for yosys. |
247+
| `VERILOG_TOP_PARAMS` | Apply toplevel params (if exist). |
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246249
#### Floorplan
247250

@@ -253,4 +256,33 @@ configuration file.
253256
| `CORE_MARGIN` | The margin between the core area and die area, in multiples of SITE heights. The margin is applied to each side. This variable is ignored if `CORE_UTILIZATION` is undefined. |
254257
| `DIE_AREA` | The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). This variable is ignored if `CORE_UTILIZATION` and `CORE_ASPECT_RATIO` are defined. |
255258
| `CORE_AREA` | The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). This variable is ignored if `CORE_UTILIZATION` and `CORE_ASPECT_RATIO` are defined. |
259+
| `RESYNTH_AREA_RECOVER` | Enable re-synthesis for area reclaim. |
260+
| `RESYNTH_TIMING_RECOVER` | Enable re-synthesis for timing optimization. |
261+
| `MACRO_HALO_X` | Set macro halo for x-direction. Only available for ASAP7 PDK. |
262+
| `MACRO_HALO_Y` | Set macro halo for y-direction. Only available for ASAP7 PDK. |
263+
264+
## Placement
265+
266+
267+
| Variable | Description |
268+
|--------------------------|----------------------------------------------------------------------------------------------------|
269+
| `MACRO_WRAPPERS` | The wrapper file that replace existing macros with their wrapped version. |
270+
271+
272+
## Clock Tree Synthesis
273+
274+
275+
| Variable | Description |
276+
|--------------------------|----------------------------------------------------------------------------------------------------|
277+
| `CTS_BUF_DISTANCE` | Distance (in microns) between buffers. |
278+
| `CTS_CLUSTER_DIAMETER` | Maximum diameter (in microns) of sink cluster. Default 20. |
279+
| `CTS_CLUSTER_SIZE` | Maximum number of sinks per cluster. Default 50.
280+
281+
282+
## Routing
283+
284+
285+
| Variable | Description |
286+
|--------------------------|----------------------------------------------------------------------------------------------------|
287+
| `FASTROUTE_TCL` | Specifies a Tcl scripts with commands to run before FastRoute. |
256288

‎etc/DependencyInstaller.sh‎

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -82,25 +82,28 @@ _installUbuntuPackages() {
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libqt5multimediawidgets5 \
8383
libqt5svg5-dev
8484

85-
lastDir="$(pwd)"
86-
87-
# temp dir to download and compile
88-
baseDir=/tmp/installers
89-
mkdir -p "${baseDir}"
90-
cd ${baseDir}
9185

9286
# install KLayout
93-
if [[ $1 == 20.04 ]]; then
94-
klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135
87+
if _versionCompare $1 -ge 23.04; then
88+
apt-get install klayout python3-pandas
9589
else
96-
klayoutChecksum=db751264399706a23d20455bb7624264
90+
if [[ $1 == 20.04 ]]; then
91+
klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135
92+
else
93+
klayoutChecksum=db751264399706a23d20455bb7624264
94+
fi
95+
lastDir="$(pwd)"
96+
# temp dir to download and compile
97+
baseDir=/tmp/installers
98+
mkdir -p "${baseDir}"
99+
cd ${baseDir}
100+
101+
wget https://www.klayout.org/downloads/Ubuntu-${1%.*}/klayout_${klayoutVersion}-1_amd64.deb
102+
md5sum -c <(echo "${klayoutChecksum} klayout_${klayoutVersion}-1_amd64.deb") || exit 1
103+
dpkg -i klayout_${klayoutVersion}-1_amd64.deb
104+
cd ${lastDir}
105+
rm -rf "${baseDir}"
97106
fi
98-
wget https://www.klayout.org/downloads/Ubuntu-${1%.*}/klayout_${klayoutVersion}-1_amd64.deb
99-
md5sum -c <(echo "${klayoutChecksum} klayout_${klayoutVersion}-1_amd64.deb") || exit 1
100-
dpkg -i klayout_${klayoutVersion}-1_amd64.deb
101-
102-
cd ${lastDir}
103-
rm -rf "${baseDir}"
104107
}
105108

106109
_installDarwinPackages() {
@@ -221,7 +224,9 @@ case "${os}" in
221224
_installUbuntuCleanUp
222225
fi
223226
if [[ "${option}" == "common" || "${option}" == "all" ]]; then
224-
_installCommon
227+
if _versionCompare ${version} -lt 23.04 ; then
228+
_installCommon
229+
fi
225230
fi
226231
;;
227232
"Darwin" )

‎flow/Makefile‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,6 @@
8080
# DESIGN_CONFIG=./designs/asap7/riscv32i/config.mk
8181
# DESIGN_CONFIG=./designs/asap7/sha3/config.mk
8282
# DESIGN_CONFIG=./designs/asap7/swerv_wrapper/config.mk
83-
# DESIGN_CONFIG=./designs/asap7/uart-blocks/config.mk
8483
# DESIGN_CONFIG=./designs/asap7/uart/config.mk
8584

8685
# DESIGN_CONFIG=./designs/intel16/aes/config.mk
@@ -350,11 +349,11 @@ $(OBJECTS_DIR)/klayout_tech.lef: $(TECH_LEF)
350349
@mkdir -p $(OBJECTS_DIR)
351350
sed '/OR_DEFAULT/d' $< > $@
352351

353-
$(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
354-
sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(SC_LEF) $(ADDITIONAL_LEFS),<lef-files>$(abspath $(file))</lef-files>),g' $< > $@
352+
$(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
353+
sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(SC_LEF) $(ADDITIONAL_LEFS),<lef-files>$(shell realpath --relative-to=$(RESULTS_DIR) $(file))</lef-files>),g' $< > $@
355354

356355
$(OBJECTS_DIR)/klayout_wrap.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
357-
sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(WRAP_LEFS),<lef-files>$(abspath $(file))</lef-files>),g' $< > $@
356+
sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(WRAP_LEFS),<lef-files>$(shell realpath --relative-to=$(OBJECTS_DIR)/def $(file))</lef-files>),g' $< > $@
358357
# Create Macro wrappers (if necessary)
359358
# ==============================================================================
360359
WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg

‎flow/designs/asap7/aes_lvt/config.mk‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
export PLATFORM = asap7
2+
3+
export DESIGN_NAME = aes_cipher_top
4+
export DESIGN_NICKNAME = aes_lvt
5+
6+
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7+
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
8+
9+
export ABC_AREA = 1
10+
11+
export CORE_UTILIZATION = 40
12+
export CORE_ASPECT_RATIO = 1
13+
export CORE_MARGIN = 2
14+
export PLACE_DENSITY = 0.65
15+
export TNS_END_PERCENT = 100
16+
17+
export ASAP7_USELVT = 1
18+
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz \
19+
$(PLATFORM_DIR)/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz \
20+
$(PLATFORM_DIR)/lib/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz \
21+
$(PLATFORM_DIR)/lib/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz \
22+
$(PLATFORM_DIR)/lib/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
23+
24+
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_R_220121a.gds
25+
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_R_1x_220121a.lef
26+
27+
export RECOVER_POWER = 20

flow/designs/asap7/uart-blocks/constraint.sdc renamed to flow/designs/asap7/aes_lvt/constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
set clk_name clk
22
set clk_port_name clk
3-
set clk_period 300
3+
set clk_period 400
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]

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