Commit 3abb7bf
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use Yosys 0.60
Signed-off-by: Eder Monteiro <[email protected]>1 parent f1df0e2 commit 3abb7bf
1 file changed
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-1
lines changed- .github/workflows/test-verific.yml+39
- CHANGELOG+9-1
- Makefile+22-5
- abc+1-1
- backends/functional/smtlib_rosette.cc+66-10
- backends/rtlil/rtlil_backend.cc+5-2
- backends/verilog/verilog_backend.cc+16-8
- docs/source/conf.py+1-1
- frontends/aiger2/xaiger.cc+2-1
- frontends/ast/ast.cc+7-2
- frontends/ast/simplify.cc+7-3
- frontends/blif/blifparse.cc+1-1
- frontends/liberty/liberty.cc+40-23
- frontends/rtlil/rtlil_frontend.cc+5
- kernel/constids.inc+2
- kernel/driver.cc+11-4
- kernel/ff.cc+286-215
- kernel/ff.h+43-35
- kernel/io.cc+1-1
- kernel/log.cc+1-1
- kernel/log.h+6-4
- kernel/register.cc+31-4
- kernel/register.h+32
- kernel/rtlil.cc+215-21
- kernel/rtlil.h+379-224
- kernel/tclapi.cc+1-1
- kernel/yosys.cc+36-10
- kernel/yosys_common.h+30-4
- libs/subcircuit/subcircuit.cc+15-1
- passes/cmds/Makefile.inc+3
- passes/cmds/icell_liberty.cc+207
- passes/cmds/sdc/Makefile.inc+3
- passes/cmds/sdc/graph-stubs.sdc+42
- passes/cmds/sdc/sdc.cc+790
- passes/fsm/fsm_detect.cc+9-2
- passes/opt/opt_clean.cc+5-1
- passes/techmap/abc.cc+2-2
- passes/techmap/abc_new.cc+2-1
- passes/techmap/libparse.cc+199-63
- pyosys/generator.py+11-6
- techlibs/common/Makefile.inc+2-1
- techlibs/common/cells.lib-108
- techlibs/common/opensta.cc+128
- techlibs/common/opensta.h+8
- techlibs/common/sdc_expand.cc+156
- techlibs/ice40/ice40_opt.cc+2-2
- techlibs/ice40/ice40_wrapcarry.cc+3-3
- techlibs/microchip/microchip_dsp.pmg+1-1
- techlibs/microchip/microchip_dsp_cascade.pmg+3-3
- techlibs/xilinx/xilinx_dsp_cascade.pmg+14-14
- tests/arch/ecp5/add_sub.py-20
- tests/arch/quicklogic/pp3/fsm.ys-2
- tests/arch/xilinx/dsp_cascade.ys+2-1
- tests/functional/rkt_vcd.py+55-8
- tests/functional/run-test.sh+4-1
- tests/functional/test_functional.py+5-3
- tests/liberty/dff.lib.verilogsim.ok+2-1
- tests/liberty/normal.lib.verilogsim.ok+16-10
- tests/liberty/read_liberty.ys+9
- tests/liberty/retention.lib+57
- tests/liberty/retention.lib.filtered.ok+42
- tests/liberty/retention.lib.verilogsim.ok+44
- tests/liberty/semicolextra.lib.verilogsim.ok+2-1
- tests/liberty/unquoted.lib.verilogsim.ok+6-3
- tests/pyosys/test_ecp5_addsub.py-1
- tests/pyosys/test_sigspec_it.py+28
- tests/rtlil/everything.v+17
- tests/sdc/alu_sub.sdc+70
- tests/sdc/alu_sub.v+62
- tests/sdc/alu_sub.ys+14
- tests/sdc/get_foo.sdc+1
- tests/sdc/run-test.sh+4
- tests/sdc/side-effects.sdc+2
- tests/sdc/side-effects.sh+4
- tests/sdc/unknown-getter.sh+5
- tests/techmap/bug5495.abc+2
- tests/techmap/bug5495.sh+12
- tests/techmap/bug5495.v+7
- tests/unit/kernel/rtlilTest.cc+30
- tests/various/bug3515.v+26
- tests/various/bug3515.ys+31
- tests/various/fsm-arst.ys+121
- tests/verilog/.gitignore+1
- tests/verilog/reset_auto_counter.ys+17
- tests/verilog/unbased_unsized.sv+25
- tests/verilog/unbased_unsized.ys+1-1
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