sdc: simplify part 2

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/asap7/ethmac/constraint.sdc

@@ -11,15 +11,15 @@ set tx_clk_name mtx_clk_pad_i
 set tx_clk_port [get_ports $tx_clk_name]
 set tx_clk_period 300
 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
-set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
+set mtx_non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
 set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
 
 set rx_clk_name mrx_clk_pad_i
 set rx_clk_port [get_ports $rx_clk_name]
 set rx_clk_period 300
 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
-set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
+set mrx_non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
 set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
 

flow/designs/asap7/ethmac_lvt/constraint.sdc

@@ -11,15 +11,15 @@ set tx_clk_name mtx_clk_pad_i
 set tx_clk_port [get_ports $tx_clk_name]
 set tx_clk_period 300
 create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
-set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
+set mtx_non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
 set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
 
 set rx_clk_name mrx_clk_pad_i
 set rx_clk_port [get_ports $rx_clk_name]
 set rx_clk_period 300
 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
-set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
+set mrx_non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
 set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]