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mock-alu: fleshing out the ALU (#1356)
* mock-alu: fleshing out the ALU - multiplier based on https://github.com/antonblanchard/vlsiffra - add, subtract and compare optimized to share resources - single barrel shifter for all shift operations - unit-tests to ensure that the ALU isn't simply empty - multiplier isn't unit-tested, not quite sure how to hook up black box tests to Chisel unit-tests. Slightly negative slack, which doesn't matter at this point. Signed-off-by: Øyvind Harboe <[email protected]> * mock-alu: add unit-testing of ASAP7 multiplier Signed-off-by: Øyvind Harboe <[email protected]> * mock-alu: docs, copy behavioral logic files from ASAP7 to run tests instead of including the files from ASAP7, provide instructions on where to copy them to run the tests. Signed-off-by: Øyvind Harboe <[email protected]> --------- Signed-off-by: Øyvind Harboe <[email protected]>
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‎flow/designs/asap7/mock-alu/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ export SDC_FILE = designs/asap7/mock-alu/constraints.sdc
99

1010
export PLATFORM = asap7
1111

12-
export PLACE_DENSITY = 0.60
13-
export CORE_UTILIZATION = 40
12+
export PLACE_DENSITY = 0.75
13+
export CORE_UTILIZATION = 50
1414
export CORE_ASPECT_RATIO = 1
1515
export CORE_MARGIN = 2
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‎flow/designs/asap7/mock-alu/constraints.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
set clk_name clock
22
set clk_port_name clock
3-
set clk_period 500
3+
set clk_period 750
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]

‎flow/designs/asap7/mock-alu/metadata-base-ok.json‎

Lines changed: 265 additions & 263 deletions
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‎flow/designs/asap7/mock-alu/rules-base.json‎

Lines changed: 4 additions & 4 deletions
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@@ -1,6 +1,6 @@
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{
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"synth__design__instance__area__stdcell": {
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"value": 217.91,
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"value": 1637.57,
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"compare": "<="
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},
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"constraints__clocks__count": {
@@ -12,7 +12,7 @@
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
15-
"value": 11523,
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"value": 13565,
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"compare": "<="
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},
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"detailedplace__design__violations": {
@@ -56,15 +56,15 @@
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"compare": "<="
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},
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"finish__timing__setup__ws": {
59-
"value": 0.0,
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"value": -50.05,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 137903,
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"compare": "<="
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},
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"finish__timing__drv__max_slew_limit": {
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"value": -0.2,
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"value": -0.86,
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"compare": ">="
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},
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"finish__timing__drv__max_fanout_limit": {

‎flow/designs/src/mock-alu/.gitignore‎

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Original file line numberDiff line numberDiff line change
@@ -5,3 +5,7 @@ target/
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.metals/
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.vscode/
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.bloop/
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test_run_dir/
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*.gtkw
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*.fir
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*.f

‎flow/designs/src/mock-alu/BarrelShifter.v‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
module BarrelShifter(
2+
input [63:0] io_data,
3+
input [5:0] io_shiftAmount,
4+
input [3:0] io_dir,
5+
output [63:0] io_out
6+
);
7+
wire _rotate_T = io_dir == 4'h5;
8+
wire [6:0] _GEN_0 = {{1'd0}, io_shiftAmount};
9+
wire [6:0] _rotate_T_2 = 7'h40 - _GEN_0;
10+
wire [6:0] rotate = _rotate_T ? _rotate_T_2 : {{1'd0}, io_shiftAmount};
11+
wire [63:0] _rotateInput_T_3 = io_data[63] ? 64'hffffffffffffffff : 64'h0;
12+
wire [63:0] _rotateInput_T_8 = 4'h7 == io_dir ? _rotateInput_T_3 : 64'h0;
13+
wire [63:0] _rotateInput_T_10 = 4'h5 == io_dir ? io_data : _rotateInput_T_8;
14+
wire [63:0] _rotateInput_T_12 = 4'h6 == io_dir ? 64'h0 : _rotateInput_T_10;
15+
wire [63:0] _rotateInput_T_14 = _rotate_T ? 64'h0 : io_data;
16+
wire [127:0] rotateInput = {_rotateInput_T_12,_rotateInput_T_14};
17+
wire [127:0] _io_out_T = rotateInput >> rotate;
18+
assign io_out = _io_out_T[63:0];
19+
endmodule

‎flow/designs/src/mock-alu/MockAlu.v‎

Lines changed: 81 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -6,37 +6,95 @@ module MockAlu(
66
input [63:0] io_b,
77
output [63:0] io_out
88
);
9+
wire [63:0] barrel_io_data;
10+
wire [5:0] barrel_io_shiftAmount;
11+
wire [3:0] barrel_io_dir;
12+
wire [63:0] barrel_io_out;
13+
wire [63:0] mult_a;
14+
wire [63:0] mult_b;
15+
wire [127:0] mult_o;
16+
wire mult_clk;
17+
wire mult_rst;
18+
wire [63:0] io_out_operand_io_a;
19+
wire [63:0] io_out_operand_io_b;
20+
wire [63:0] io_out_operand_io_out;
21+
wire [63:0] io_out_operand_1_io_a;
22+
wire [63:0] io_out_operand_1_io_b;
23+
wire [63:0] io_out_operand_1_io_out;
24+
wire [63:0] io_out_operand_2_io_a;
25+
wire [63:0] io_out_operand_2_io_b;
26+
wire [63:0] io_out_operand_2_io_out;
927
reg [3:0] op;
1028
reg [63:0] a;
1129
reg [63:0] b;
12-
wire [63:0] _out_T_1 = a + b;
13-
wire [63:0] _out_T_3 = a - b;
14-
wire [63:0] _out_T_4 = a & b;
15-
wire [63:0] _out_T_5 = a | b;
16-
wire [63:0] _out_T_6 = a ^ b;
17-
wire _out_T_16 = a <= b;
18-
wire _GEN_1 = 4'hb == op ? a < b : _out_T_16;
19-
wire _GEN_2 = 4'hc == op ? $signed(a) <= $signed(b) : _GEN_1;
20-
wire _GEN_3 = 4'ha == op ? $signed(a) < $signed(b) : _GEN_2;
21-
wire _GEN_4 = 4'h9 == op ? a != b : _GEN_3;
22-
wire _GEN_5 = 4'h8 == op ? a == b : _GEN_4;
23-
wire [63:0] _GEN_6 = 4'h4 == op ? _out_T_6 : {{63'd0}, _GEN_5};
24-
reg [63:0] io_out_REG;
25-
assign io_out = io_out_REG;
30+
wire isSubtraction = op == 4'h1 | op == 4'h8 | op == 4'h9 | op == 4'ha | op == 4'hc | op == 4'hb | op == 4'hd;
31+
wire [63:0] _modifiedB_T = ~b;
32+
wire [63:0] modifiedB = isSubtraction ? _modifiedB_T : b;
33+
wire [64:0] _extendedResult_T = a + modifiedB;
34+
wire [64:0] _GEN_0 = {{64'd0}, isSubtraction};
35+
wire [65:0] _extendedResult_T_1 = _extendedResult_T + _GEN_0;
36+
wire [64:0] extendedResult = _extendedResult_T_1[64:0];
37+
wire [63:0] result = extendedResult[63:0];
38+
wire carryOut = extendedResult[64];
39+
wire isTrueZero = ~(|result);
40+
wire isNegative = result[63];
41+
wire _io_out_T_1 = ~isTrueZero;
42+
wire _io_out_T_2 = isTrueZero | isNegative;
43+
wire _io_out_T_3 = ~carryOut;
44+
wire _io_out_T_5 = isTrueZero | _io_out_T_3;
45+
wire [63:0] _io_out_T_22 = 4'h2 == op ? io_out_operand_io_out : 64'h0;
46+
wire [63:0] _io_out_T_24 = 4'h3 == op ? io_out_operand_1_io_out : _io_out_T_22;
47+
wire [63:0] _io_out_T_26 = 4'h4 == op ? io_out_operand_2_io_out : _io_out_T_24;
48+
wire [63:0] _io_out_T_28 = 4'h0 == op ? result : _io_out_T_26;
49+
wire [63:0] _io_out_T_30 = 4'h1 == op ? result : _io_out_T_28;
50+
wire [63:0] _io_out_T_32 = 4'h8 == op ? {{63'd0}, isTrueZero} : _io_out_T_30;
51+
wire [63:0] _io_out_T_34 = 4'h9 == op ? {{63'd0}, _io_out_T_1} : _io_out_T_32;
52+
wire [63:0] _io_out_T_36 = 4'ha == op ? {{63'd0}, isNegative} : _io_out_T_34;
53+
wire [63:0] _io_out_T_38 = 4'hc == op ? {{63'd0}, _io_out_T_2} : _io_out_T_36;
54+
wire [63:0] _io_out_T_40 = 4'hb == op ? {{63'd0}, _io_out_T_3} : _io_out_T_38;
55+
wire [63:0] _io_out_T_42 = 4'hd == op ? {{63'd0}, _io_out_T_5} : _io_out_T_40;
56+
wire [63:0] _io_out_T_44 = 4'h5 == op ? barrel_io_out : _io_out_T_42;
57+
wire [63:0] _io_out_T_46 = 4'h6 == op ? barrel_io_out : _io_out_T_44;
58+
wire [63:0] _io_out_T_48 = 4'h7 == op ? barrel_io_out : _io_out_T_46;
59+
reg [127:0] io_out_REG;
60+
BarrelShifter barrel (
61+
.io_data(barrel_io_data),
62+
.io_shiftAmount(barrel_io_shiftAmount),
63+
.io_dir(barrel_io_dir),
64+
.io_out(barrel_io_out)
65+
);
66+
multiplier mult (
67+
.a(mult_a),
68+
.b(mult_b),
69+
.o(mult_o),
70+
.clk(mult_clk),
71+
.rst(mult_rst)
72+
);
73+
assign io_out_operand_io_out = io_out_operand_io_a & io_out_operand_io_b;
74+
assign io_out_operand_1_io_out = io_out_operand_1_io_a | io_out_operand_1_io_b;
75+
assign io_out_operand_2_io_out = io_out_operand_2_io_a ^ io_out_operand_2_io_b;
76+
assign io_out = io_out_REG[63:0];
77+
assign barrel_io_data = a;
78+
assign barrel_io_shiftAmount = b[5:0];
79+
assign barrel_io_dir = io_op;
80+
assign mult_a = a;
81+
assign mult_b = b;
82+
assign mult_clk = clock;
83+
assign mult_rst = reset;
84+
assign io_out_operand_io_a = a;
85+
assign io_out_operand_io_b = b;
86+
assign io_out_operand_1_io_a = a;
87+
assign io_out_operand_1_io_b = b;
88+
assign io_out_operand_2_io_a = a;
89+
assign io_out_operand_2_io_b = b;
2690
always @(posedge clock) begin
2791
op <= io_op;
2892
a <= io_a;
2993
b <= io_b;
30-
if (4'h0 == op) begin
31-
io_out_REG <= _out_T_1;
32-
end else if (4'h1 == op) begin
33-
io_out_REG <= _out_T_3;
34-
end else if (4'h2 == op) begin
35-
io_out_REG <= _out_T_4;
36-
end else if (4'h3 == op) begin
37-
io_out_REG <= _out_T_5;
94+
if (4'he == op) begin
95+
io_out_REG <= mult_o;
3896
end else begin
39-
io_out_REG <= _GEN_6;
97+
io_out_REG <= {{64'd0}, _io_out_T_48};
4098
end
4199
end
42100
endmodule

‎flow/designs/src/mock-alu/build.sbt‎

Lines changed: 43 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,12 @@ organization := "edu.berkeley.cs"
55

66
scalaVersion := "2.13.6"
77

8-
scalacOptions ++= Seq("-deprecation", "-feature", "-unchecked", "-language:reflectiveCalls")
8+
scalacOptions ++= Seq(
9+
"-deprecation",
10+
"-feature",
11+
"-unchecked",
12+
"-language:reflectiveCalls"
13+
)
914

1015
val defaultVersions = Map(
1116
"chisel3" -> "3.6.0-RC2",
@@ -14,14 +19,49 @@ val defaultVersions = Map(
1419

1520
libraryDependencies ++= (Seq("chisel3", "chiseltest").map { dep: String =>
1621
"edu.berkeley.cs" %% dep % sys.props
17-
.getOrElse(dep + "Version", defaultVersions(dep)) withSources () withJavadoc ()
22+
.getOrElse(
23+
dep + "Version",
24+
defaultVersions(dep)
25+
) withSources () withJavadoc ()
1826
})
1927

20-
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0-RC2" cross CrossVersion.full)
28+
addCompilerPlugin(
29+
"edu.berkeley.cs" % "chisel3-plugin" % "3.6.0-RC2" cross CrossVersion.full
30+
)
2131

2232
libraryDependencies += "com.github.scopt" %% "scopt" % "4.0.0"
2333

2434
resolvers ++= Seq(
2535
Resolver.sonatypeRepo("snapshots"),
2636
Resolver.sonatypeRepo("releases")
2737
)
38+
39+
val verilatorRoot = sys.env.get("VERILATOR_ROOT") match {
40+
case Some(path) => path
41+
case None => "dummy"
42+
}
43+
44+
val verilatorBin = f"$verilatorRoot/bin"
45+
46+
lazy val printVerilatorBin = taskKey[Unit]("Print verilatorBin")
47+
48+
printVerilatorBin := {
49+
println("verilatorBin=" + verilatorBin)
50+
}
51+
52+
val path = sys.env.get("PATH") match {
53+
case Some(path) => f"$verilatorBin:$path"
54+
case None => verilatorBin
55+
}
56+
onLoad in Global := {
57+
println("verilatorBin=" + verilatorBin)
58+
println("path=" + path)
59+
(onLoad in Global).value
60+
}
61+
62+
Test / envVars := Map(
63+
"PATH" -> path,
64+
"VERILATOR_ROOT" -> verilatorRoot
65+
)
66+
67+
fork := true

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