Merge remote-tracking branch 'private/master' into secure-gpl-filler-gcell-removal

Author: gudeh

docs/user/FlowVariables.md

@@ -223,6 +223,7 @@ configuration file.
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
 | <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
+| <a name="SYNTH_HIER_SEPARATOR"></a>SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| |
 | <a name="SYNTH_KEEP_MODULES"></a>SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
 | <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| |
@@ -464,6 +465,7 @@ configuration file.
 - [SET_RC_TCL](#SET_RC_TCL)
 - [SLEW_MARGIN](#SLEW_MARGIN)
 - [SYNTH_ARGS](#SYNTH_ARGS)
+- [SYNTH_HIER_SEPARATOR](#SYNTH_HIER_SEPARATOR)
 - [TAP_CELL_NAME](#TAP_CELL_NAME)
 - [TECH_LEF](#TECH_LEF)
 - [USE_FILL](#USE_FILL)

etc/DependencyInstaller.sh

@@ -170,7 +170,7 @@ _installUbuntuPackages() {
         fi
         else
             if [[ $1 == 20.04 ]]; then
-                klayoutChecksum=15a26f74cf396d8a10b7985ed70ab135
+                klayoutChecksum=f78d41edf5bcfa5f1990bde1a9307e9e
             else
                 klayoutChecksum=54748a49e1ab53e14cf5bf95feb2f25a
             fi

flow/Makefile

@@ -184,17 +184,9 @@ $(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKN
 .PHONY: versions.txt
 versions.txt:
 	mkdir -p $(OBJECTS_DIR)
-	@if [ -z "$(YOSYS_EXE)" ]; then \
-		echo >> $(OBJECTS_DIR)/$@ "yosys not installed"; \
-	else \
-		$(YOSYS_EXE) -V > $(OBJECTS_DIR)/$@; \
-	fi
-	@echo openroad `$(OPENROAD_EXE) -version` >> $(OBJECTS_DIR)/$@
-	@if [ -z "$(KLAYOUT_CMD)" ]; then \
-		echo >> $(OBJECTS_DIR)/$@ "klayout not installed"; \
-	else \
-		$(KLAYOUT_CMD) -zz -v >> $(OBJECTS_DIR)/$@; \
-	fi
+	@echo "yosys $(if $(YOSYS_EXE),$(shell $(YOSYS_EXE) -V 2>&1),not available)" > $(OBJECTS_DIR)/$@
+	@echo "openroad $(if $(OPENROAD_EXE),$(shell $(OPENROAD_EXE) -version 2>&1),not available)" >> $(OBJECTS_DIR)/$@
+	@echo "klayout $(if $(KLAYOUT_CMD),$(shell $(KLAYOUT_CMD) -zz -v 2>&1),not available)" >> $(OBJECTS_DIR)/$@
 
 # Pre-process libraries
 # ==============================================================================

flow/designs/asap7/cva6/config.mk

@@ -88,10 +88,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \
 
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 
-export CORE_UTILIZATION       = 50
+export CORE_UTILIZATION       = 70
 export CORE_MARGIN            = 2
-export MACRO_HALO             = 5
-export PLACE_DENSITY          = 0.64
+export MACRO_PLACE_HALO       = 3 3
+export PLACE_DENSITY          = 0.73
 
 # a smoketest for this option, there are a
 # few last gasp iterations

flow/designs/asap7/cva6/constraint.sdc

@@ -3,7 +3,7 @@
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
-set clk_period 1300
+set clk_period 1200
 set input_delay 0.46
 set output_delay 0.11
 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

flow/designs/asap7/cva6/rules-base.json

@@ -8,31 +8,31 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 20743,
+        "value": 20690,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 137118,
+        "value": 136421,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 11923,
+        "value": 11863,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 11923,
+        "value": 11863,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1124948,
+        "value": 1074578,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -68.36,
+        "value": -139.89,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 20933,
+        "value": 20850,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 5962,
+        "value": 5931,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.27,
+        "value": -10.0,
         "compare": ">="
     }
 }

flow/designs/gf12/bp_single/rules-base.json

@@ -8,35 +8,35 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 509289,
+        "value": 491681,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 546190,
+        "value": 535708,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 47495,
+        "value": 46583,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 47495,
+        "value": 46583,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 7863419,
+        "value": 6200511,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
-        "value": 1,
+        "value": 0,
         "compare": "<="
     },
     "detailedroute__antenna__violating__nets": {
@@ -48,19 +48,19 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -183.6,
+        "value": -144.83,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 519153,
+        "value": 500408,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 23747,
+        "value": 23292,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 230,
+        "value": 479,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {

flow/scripts/synth.tcl

@@ -17,6 +17,10 @@ if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} {
   }
 }
 
+if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} {
+  scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
+}
+
 set synth_full_args $::env(SYNTH_ARGS)
 if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
   set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]

flow/scripts/variables.yaml

@@ -684,6 +684,10 @@ SYNTH_ARGS:
   description: |
     Optional synthesis variables for yosys.
   default: -flatten
+SYNTH_HIER_SEPARATOR:
+  description: |
+    Separator used for the synthesis flatten stage.
+  default: .
 VERILOG_TOP_PARAMS:
   description: |
     Apply toplevel params (if exist).