floorplan: use 2_floorplan.sdc in floorplan, written by floorplan.tcl

Since floorplan.tcl can do retiming, it is important to use post
retiming .sdc file in subsequent steps to avoid incorrect
timing information

fixes #2485

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/scripts/io_placement_random.tcl

@@ -2,7 +2,7 @@ source $::env(SCRIPTS_DIR)/load.tcl
 erase_non_stage_variables floorplan
 
 if {![env_var_equals IS_CHIP 1]} {
-  load_design 2_1_floorplan.odb 1_synth.sdc
+  load_design 2_1_floorplan.odb 2_floorplan.sdc
   lappend ::env(PLACE_PINS_ARGS) -random
   source $::env(SCRIPTS_DIR)/io_placement_util.tcl
   write_db $::env(RESULTS_DIR)/2_2_floorplan_io.odb

flow/scripts/macro_place.tcl

@@ -1,6 +1,6 @@
 source $::env(SCRIPTS_DIR)/load.tcl
 erase_non_stage_variables floorplan
-load_design 2_3_floorplan_tdms.odb 1_synth.sdc
+load_design 2_3_floorplan_tdms.odb 2_floorplan.sdc
 
 source $::env(SCRIPTS_DIR)/macro_place_util.tcl
 

flow/scripts/pdn.tcl

@@ -1,6 +1,6 @@
 source $::env(SCRIPTS_DIR)/load.tcl
 erase_non_stage_variables floorplan
-load_design 2_5_floorplan_tapcell.odb 1_synth.sdc
+load_design 2_5_floorplan_tapcell.odb 2_floorplan.sdc
 
 source $::env(PDN_TCL)
 pdngen

flow/scripts/tapcell.tcl

@@ -1,7 +1,7 @@
 source $::env(SCRIPTS_DIR)/load.tcl
 erase_non_stage_variables floorplan
 
-load_design 2_4_floorplan_macro.odb 1_synth.sdc
+load_design 2_4_floorplan_macro.odb 2_floorplan.sdc
 
 if {[env_var_exists_and_non_empty TAPCELL_TCL]} {
     source $::env(TAPCELL_TCL)

flow/scripts/tdms_place.tcl

@@ -20,7 +20,7 @@ proc find_macros {} {
 if {!([env_var_exists_and_non_empty MACRO_PLACEMENT] ||
       [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL]) &&
     ![env_var_equals RTLMP_FLOW 1]} {
-  load_design 2_2_floorplan_io.odb 1_synth.sdc
+  load_design 2_2_floorplan_io.odb 2_floorplan.sdc
 
   set_dont_use $::env(DONT_USE_CELLS)