@@ -640,17 +640,17 @@ endef
640640
641641# STEP 1: Translate verilog to odb
642642# -------------------------------------------------------------------------------
643- $(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan))
643+ $(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $( TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan))
644644
645645$(eval $(call do-step,2_2_floorplan_io,$(RESULTS_DIR)/2_1_floorplan.odb $(IO_CONSTRAINTS),io_placement_random))
646646
647647# STEP 3: Timing Driven Mixed Sized Placement
648648# -------------------------------------------------------------------------------
649- $(eval $(call do-step,2_3_floorplan_tdms,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(LIB_FILES),tdms_place))
649+ $(eval $(call do-step,2_3_floorplan_tdms,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $( LIB_FILES),tdms_place))
650650
651651# STEP 4: Macro Placement
652652# -------------------------------------------------------------------------------
653- $(eval $(call do-step,2_4_floorplan_macro,$(RESULTS_DIR)/2_3_floorplan_tdms.odb $(RESULTS_DIR)/1_synth.v $(MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place))
653+ $(eval $(call do-step,2_4_floorplan_macro,$(RESULTS_DIR)/2_3_floorplan_tdms.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $( MACRO_PLACEMENT) $(MACRO_PLACEMENT_TCL),macro_place))
654654
655655# STEP 5: Tapcell and Welltie insertion
656656# -------------------------------------------------------------------------------
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