synth: Pipe VERILOG_DEFINES

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/designs/asap7/cva6/config.mk

@@ -1,7 +1,3 @@
-#
-# TODO before enablement: pipe VERILOG_DEFINES through to yosys
-#
-
 export PLATFORM               = asap7
 
 export DESIGN_NAME            = cva6

flow/scripts/synth_preamble.tcl

@@ -52,9 +52,12 @@ if {[env_var_exists_and_non_empty RTLIL_FILE]} {
     # Workaround for yosys-slang#119
     setattr -unset init
   } else {
+    verilog_defaults -push
+    verilog_defaults -add {*}$::env(VERILOG_DEFINES)
     foreach file $::env(VERILOG_FILES) {
       read_verilog -defer -sv {*}$vIdirsArgs $file
     }
+    verilog_defaults -pop
   }
 
   # Read platform specific mapfile for OPENROAD_CLKGATE cells

flow/scripts/variables.yaml

@@ -575,6 +575,13 @@ VERILOG_FILES:
     The path to the design Verilog files providing a description of modules.
   stages:
     - synth
+VERILOG_DEFINES:
+  description: >
+    Preprocessor defines passed to the language frontend.
+    Example: `-D HPDCACHE_ASSERT_OFF`
+  default: ""
+  stages:
+    - synth
 SDC_FILE:
   required: true
   description: |