synth: Add SYNTH_USE_SLANG option

Add option to read the design via yosys-slang. Reorder read_liberty
ahead of design read-in so that Liberty cell definitions are
available when elaborating.

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/scripts/synth.tcl

@@ -1,4 +1,4 @@
-set ::env(VERILOG_FILES) $::env(RESULTS_DIR)/1_synth.rtlil
+set ::env(RTLIL_FILE) $::env(RESULTS_DIR)/1_synth.rtlil
 
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 

flow/scripts/synth_preamble.tcl

@@ -21,38 +21,52 @@ if {[env_var_exists_and_non_empty SYNTH_NETLIST_FILES]} {
   exit
 }
 
-# Setup verilog include directories
-set vIdirsArgs ""
-if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
-  foreach dir $::env(VERILOG_INCLUDE_DIRS) {
-    lappend vIdirsArgs "-I$dir"
-  }
-  set vIdirsArgs [join $vIdirsArgs]
-}
-
-
-# Read verilog files
-foreach file $::env(VERILOG_FILES) {
-  if {[file extension $file] == ".rtlil"} {
-    read_rtlil $file
-  } elseif {[file extension $file] == ".json"} {
+# Read design
+if {[env_var_exists_and_non_empty RTLIL_FILE]} {
+  # We are reading a Yosys checkpoint
+  set file $env(RTLIL_FILE)
+  if {[file extension $file] == ".json"} {
     read_json $file
   } else {
-    read_verilog -defer -sv {*}$vIdirsArgs $file
+    read_rtlil $file
+  }
+} else {
+  # We are reading Verilog sources
+  source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
+
+  # Setup verilog include directories
+  set vIdirsArgs ""
+  if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
+    foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+      lappend vIdirsArgs "-I$dir"
+    }
+    set vIdirsArgs [join $vIdirsArgs]
   }
-}
 
-source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
+  if {[env_var_exists_and_non_empty SYNTH_USE_SLANG]} {
+    # slang requires all files at once
+    plugin -i slang
+    yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \
+      --ignore-assertions --top $::env(DESIGN_NAME) \
+      {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env(VERILOG_DEFINES)
+    # Workaround for yosys-slang#119
+    setattr -unset init
+  } else {
+    foreach file $::env(VERILOG_FILES) {
+      read_verilog -defer -sv {*}$vIdirsArgs $file
+    }
+  }
 
-# Read platform specific mapfile for OPENROAD_CLKGATE cells
-if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} {
-  read_verilog -defer $::env(CLKGATE_MAP_FILE)
-}
+  # Read platform specific mapfile for OPENROAD_CLKGATE cells
+  if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} {
+    read_verilog -defer $::env(CLKGATE_MAP_FILE)
+  }
 
-if {[env_var_exists_and_non_empty SYNTH_BLACKBOXES]} {
-  hierarchy -check -top $::env(DESIGN_NAME)
-  foreach m $::env(SYNTH_BLACKBOXES) {
-    blackbox $m
+  if {[env_var_exists_and_non_empty SYNTH_BLACKBOXES]} {
+    hierarchy -check -top $::env(DESIGN_NAME)
+    foreach m $::env(SYNTH_BLACKBOXES) {
+      blackbox $m
+    }
   }
 }
 

flow/scripts/variables.yaml

@@ -169,6 +169,9 @@ SYNTH_MEMORY_MAX_BITS:
   default: 4096
   stages:
     - synth
+SYNTH_USE_SLANG:
+  description: >
+    Use yosys-slang for read-in of SystemVerilog design.
 SYNTH_BLACKBOXES:
   description: >
     List of cells treated as a black box by Yosys. With Bazel, this can be used
@@ -569,8 +572,7 @@ DESIGN_NAME:
 VERILOG_FILES:
   required: true
   description: >
-    The path to the design Verilog files or JSON files providing a description
-    of modules (check `yosys -h write_json` for more details).
+    The path to the design Verilog files providing a description of modules.
   stages:
     - synth
 SDC_FILE: