Merge pull request #1215 from The-OpenROAD-Project-staging/asap7@updateMem

Update + Add - LEF, LIB and Verilog models for fakeram* and fakereg*

Author: maliberty

flow/platforms/asap7/lef/fakeram7_2048x39.lef

@@ -2241,7 +2241,7 @@ MACRO fakeram7_2048x39
     LAYER M3 ;
     RECT 0 0 5.130 532.000 ;
     LAYER M4 ;
-    RECT 0 0 5.130 532.000 ;
+    RECT 0.1 0 5.030 532.000 ;
   END
 END fakeram7_2048x39
 

flow/platforms/asap7/lef/fakeram7_256x32.lef

@@ -877,7 +877,7 @@ MACRO fakeram7_256x32
     LAYER M3 ;
     RECT 0 0 4.180 67.200 ;
     LAYER M4 ;
-    RECT 0 0 4.180 67.200 ;
+    RECT 0.1 0 4.080 67.200 ;
   END
 END fakeram7_256x32
 

flow/platforms/asap7/lef/fakeram7_256x34.lef

@@ -913,7 +913,7 @@ MACRO fakeram7_256x34
     LAYER M3 ;
     RECT 0 0 4.560 67.200 ;
     LAYER M4 ;
-    RECT 0 0 4.560 67.200 ;
+    RECT 0.1 0 4.460 67.200 ;
   END
 END fakeram7_256x34
 

flow/platforms/asap7/lef/fakeram7_64x21.lef

@@ -530,7 +530,7 @@ MACRO fakeram7_64x21
     LAYER M3 ;
     RECT 0 0 2.850 16.800 ;
     LAYER M4 ;
-    RECT 0 0 2.850 16.800 ;
+    RECT 0.1 0 2.750 16.800 ;
   END
 END fakeram7_64x21