merge master

eder-matheus · eder-matheus · commit 446b94cbc018 · 2024-10-04T02:56:27.000Z
diff --git a/docs/user/InstructionsForAutoTuner.md b/docs/user/InstructionsForAutoTuner.md
@@ -27,6 +27,10 @@ We have provided two convenience scripts, `./install.sh` and `./setup.sh`
 that works in Python3.8 for installation and configuration of AutoTuner,
 as shown below:
 
+```{note}
+Make sure you run the following commands in `./tools/AutoTuner/src/autotuner`.
+```
+
 ```shell
 # Install prerequisites
 ./tools/AutoTuner/install.sh
@@ -127,8 +131,8 @@ Example:
 
 ```shell
 python3 distributed.py --design gcd --platform sky130hd \
-                       --config ../designs/sky130hd/gcd/autotuner.json \
-                       tune
+                       --config ../../../../flow/designs/sky130hd/gcd/autotuner.json \
+                       tune --samples 5
 ```
 #### Sweep only 
 
diff --git a/flow/Makefile b/flow/Makefile
@@ -218,11 +218,6 @@ export OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_
 export REPORTS_DIR = $(WORK_HOME)/reports/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
 export RESULTS_DIR = $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
 
-# BLOCKS is ORFS specific and is used to trigger hierarchical flow,
-# MACROS is a space separated list of macros used in the design,
-# but not necessarily built by ORFS using the BLOCKS mechanism.
-export MACROS ?= $(BLOCKS)
-
 ifneq ($(BLOCKS),)
   $(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
   $(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib))
diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk
@@ -11,4 +11,3 @@ export CORE_MARGIN            = 2
 export PLACE_DENSITY          = 0.70
 
 export PLACE_PINS_ARGS = -annealing
-export HAS_IO_CONSTRAINTS = 0
diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk
@@ -15,10 +15,8 @@ export PLACE_DENSITY          = 0.65
 
 export BLOCKS ?= aes_rcon aes_sbox
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 export PLACE_PINS_ARGS = -annealing
-export HAS_IO_CONSTRAINTS = 0
 
 # Generous routing at top level
 export MIN_ROUTING_LAYER      = M2
diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = riscv_top
 export PLATFORM    = asap7
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 export RTLMP_MIN_INST = 1000
 export RTLMP_MAX_INST = 3500
diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk
@@ -2,7 +2,6 @@ export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = asap7
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
 export RTLMP_MIN_INST = 5000
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
@@ -3,7 +3,6 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 10000
-export RTLMP_FLOW = 1
 #
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \
diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk
@@ -4,7 +4,6 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 10000
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 
diff --git a/flow/designs/gf12/bp_dual/config.mk b/flow/designs/gf12/bp_dual/config.mk
@@ -4,7 +4,6 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 #
-export RTLMP_FLOW = 1
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
 export RTLMP_MIN_INST = 10000
diff --git a/flow/designs/gf12/bp_quad/config.mk b/flow/designs/gf12/bp_quad/config.mk
@@ -2,7 +2,6 @@ export DESIGN_NICKNAME = bp_quad
 export DESIGN_NAME = bsg_chip
 export PLATFORM    = gf12
 
-export RTLMP_FLOW = 1
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 1000
 
diff --git a/flow/designs/gf12/bp_single/config_mpl2.mk b/flow/designs/gf12/bp_single/config_mpl2.mk
@@ -6,7 +6,6 @@ export SKIP_GATE_CLONING = 1
 export TNS_END_PERCENT = 5
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/gf12/ca53/config.mk b/flow/designs/gf12/ca53/config.mk
@@ -1,7 +1,6 @@
 export DESIGN_NAME = ca53_cpu
 export PLATFORM    = gf12
 
-export RTLMP_FLOW = 1
 
 export VERILOG_FILES  = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
 export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk
@@ -3,7 +3,6 @@ export PLATFORM    = gf12
 #
 export MAX_UNGROUP_SIZE ?= 10000
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 25000
diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk
@@ -4,7 +4,6 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 1000
-export RTLMP_FLOW = 1
 
 export VERILOG_FILES  = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
                         ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \
diff --git a/flow/designs/gf180/uart-blocks/config.mk b/flow/designs/gf180/uart-blocks/config.mk
@@ -7,7 +7,6 @@ export VERILOG_FILES = ./designs/src/uart-no-param/*.v
 export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 export BLOCKS = uart_rx
 
 export DIE_AREA = 0 0 430 430
diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NICKNAME = ariane133
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NICKNAME = ariane136
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = black_parrot
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_be_top/config.mk b/flow/designs/nangate45/bp_be_top/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bp_be_top
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bp_fe_top
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bp_multi_top
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_quad/config.mk b/flow/designs/nangate45/bp_quad/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NICKNAME = bp_quad
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 #export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/mempool_group/config.mk b/flow/designs/nangate45/mempool_group/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NICKNAME = mempool_group
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW ?= True
 
 export TEMP_DESIGN_DIR = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)
 export VERILOG_FILES = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v
diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk
@@ -2,7 +2,6 @@ export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/tinyRocket/config.mk b/flow/designs/nangate45/tinyRocket/config.mk
@@ -4,7 +4,6 @@ export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 5000
-export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
                        ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \
diff --git a/flow/designs/sky130hd/coyote_tc/config.mk b/flow/designs/sky130hd/coyote_tc/config.mk
@@ -7,7 +7,6 @@ export PLATFORM    = sky130hd
 #
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 export SKY130_IO_VERSION ?= v0.2.0
 export OPENRAMS_DIR = ./platforms/sky130ram
diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk
@@ -22,7 +22,6 @@ export ADDITIONAL_LEFS  = $(wildcard $(microwatt_DIR)/lef/*.lef)
 export ADDITIONAL_LIBS = $(wildcard $(microwatt_DIR)/lib/*.lib)
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 export RTLMP_BOUNDARY_WT = 0
 export MACRO_PLACE_HALO = 100 100
diff --git a/flow/designs/sky130hd_fakestack/ariane136/config.mk b/flow/designs/sky130hd_fakestack/ariane136/config.mk
@@ -4,7 +4,6 @@ export PLATFORM    = sky130hd_fakestack
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE = 10000
-export RTLMP_FLOW = 1
 
 export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/src/mock-alu/defaults.mk b/flow/designs/src/mock-alu/defaults.mk
@@ -16,4 +16,3 @@ verilog:
 	./designs/src/mock-alu/verilog.sh
 
 export PLACE_PINS_ARGS=-annealing
-export HAS_IO_CONSTRAINTS=0
diff --git a/flow/designs/tsmc65lp/ariane/config.mk b/flow/designs/tsmc65lp/ariane/config.mk
@@ -2,7 +2,6 @@ export DESIGN_NAME = ariane
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
diff --git a/flow/designs/tsmc65lp/black_parrot/config.mk b/flow/designs/tsmc65lp/black_parrot/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = black_parrot
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/tsmc65lp/bp_be_top/config.mk b/flow/designs/tsmc65lp/bp_be_top/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bp_be_top
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
diff --git a/flow/designs/tsmc65lp/bp_fe_top/config.mk b/flow/designs/tsmc65lp/bp_fe_top/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bp_fe_top
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
@@ -25,7 +24,6 @@ export ADDITIONAL_GDS  = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w8_bit.gds2 \
 export DIE_AREA    = 0 0 880 780 
 export CORE_AREA   = 10 12 870 770
 export PLACE_PINS_ARGS = -exclude left:* -exclude right:0-400 -exclude bottom:*
-export HAS_IO_CONSTRAINTS = 0
 
 export MACRO_PLACE_HALO = 10 10
 export MACRO_PLACE_CHANNEL = 20 20
diff --git a/flow/designs/tsmc65lp/bp_multi_top/config.mk b/flow/designs/tsmc65lp/bp_multi_top/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bp_multi_top
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/tsmc65lp/coyote/config.mk b/flow/designs/tsmc65lp/coyote/config.mk
@@ -3,7 +3,6 @@ export DESIGN_NAME = bsg_rocket_node_client_rocc
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 
 # RTL_MP Settings
diff --git a/flow/designs/tsmc65lp/swerv_wrapper/config.mk b/flow/designs/tsmc65lp/swerv_wrapper/config.mk
@@ -2,7 +2,6 @@ export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/tsmc65lp/tinyRocket/config.mk b/flow/designs/tsmc65lp/tinyRocket/config.mk
@@ -4,7 +4,6 @@ export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 5000
-export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
                        ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \
diff --git a/flow/designs/tsmc65lp/vanilla5/config.mk b/flow/designs/tsmc65lp/vanilla5/config.mk
@@ -17,7 +17,6 @@ export ADDITIONAL_GDS  = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_all.gds2 \
 
 export SYNTH_HIERARCHICAL = 1
 
-export RTLMP_FLOW = 1
 
 # These values must be multiples of placement site
 export DIE_AREA    = 0 0 1100 400.8
diff --git a/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl b/flow/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl
@@ -1,4 +1,5 @@
 # Top level PDN for macros using BLOCK_grid_strategy.tcl
+source $::env(SCRIPTS_DIR)/util.tcl
 
 ####################################
 # global connections
@@ -30,7 +31,16 @@ add_pdn_connect -grid {top} -layers {M5 M6}
 # Element grid
 ####################################
 # The halo around the macro prevents pdn from blocking pin access
-define_pdn_grid -macro -cells $::env(MACROS) \
+
+set macro_names {}
+
+foreach macro [find_macros] {
+  set macro_name [[$macro getMaster] getName]
+  dict set macro_names $macro_name 1
+}
+set macro_names [dict keys $macro_names]
+
+define_pdn_grid -macro -cells $macro_names \
     -halo "$::env(MACRO_HALO_X) $::env(MACRO_HALO_Y) $::env(MACRO_HALO_X) $::env(MACRO_HALO_Y)" \
     -voltage_domains {CORE} -name ElementGrid
 
diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl
@@ -1,19 +1,3 @@
-proc find_macros {} {
-  set macros ""
-
-  set db [ord::get_db]
-  set block [[$db getChip] getBlock]
-  foreach inst [$block getInsts] {
-    set inst_master [$inst getMaster]
-
-    # BLOCK means MACRO cells
-    if { [string match [$inst_master getType] "BLOCK"] } {
-      append macros " " $inst
-    }
-  }
-  return $macros
-}
-
 if {[find_macros] != ""} {
 # If wrappers defined replace macros with their wrapped version
 # # ----------------------------------------------------------------------------
diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl
@@ -83,3 +83,19 @@ proc append_env_var {list_name var_name prefix has_arg} {
     }
   }
 }
+
+proc find_macros {} {
+  set macros ""
+
+  set db [ord::get_db]
+  set block [[$db getChip] getBlock]
+  foreach inst [$block getInsts] {
+    set inst_master [$inst getMaster]
+
+    # BLOCK means MACRO cells
+    if { [string match [$inst_master getType] "BLOCK"] } {
+      append macros " " $inst
+    }
+  }
+  return $macros
+}
diff --git a/flow/util/distributed.py b/flow/util/distributed.py

Original file line number	Diff line number	Diff line change
`@@ -11,4 +11,3 @@ export CORE_MARGIN = 2`
`11`	`11`	`export PLACE_DENSITY = 0.70`
`12`	`12`
`13`	`13`	`export PLACE_PINS_ARGS = -annealing`
`14`		`-export HAS_IO_CONSTRAINTS = 0`
Original file line number	Diff line number	Diff line change
`@@ -3,7 +3,6 @@ export PLATFORM = gf12`
`3`	`3`
`4`	`4`	`export SYNTH_HIERARCHICAL = 1`
`5`	`5`	`export MAX_UNGROUP_SIZE ?= 10000`
`6`		`-export RTLMP_FLOW = 1`
`7`	`6`	`#`
`8`	`7`
`9`	`8`	`export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \`
Original file line number	Diff line number	Diff line change
`@@ -4,7 +4,6 @@ export PLATFORM = gf12`
`4`	`4`
`5`	`5`	`export SYNTH_HIERARCHICAL = 1`
`6`	`6`	`export MAX_UNGROUP_SIZE ?= 10000`
`7`		`-export RTLMP_FLOW = 1`
`8`	`7`	`#`
`9`	`8`	`# RTL_MP Settings`
`10`	`9`