Enable mpl2 for vanilla5

Signed-off-by: Matt Liberty <[email protected]>

Author: maliberty

flow/designs/tsmc65lp/vanilla5/config.mk

@@ -15,6 +15,10 @@ export ADDITIONAL_GDS  = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_all.gds2 \
                          $(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg5_w32_all.gds2 \
                          $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_byte.gds2
 
+export SYNTH_HIERARCHICAL = 1
+
+export RTLMP_FLOW = True
+
 # These values must be multiples of placement site
 export DIE_AREA    = 0 0 1100 400.8
 export CORE_AREA   = 10 12 1090 391.2

flow/designs/tsmc65lp/vanilla5/metadata-base-ok.json

@@ -0,0 +1,354 @@
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+  "constraints__clocks__details": [
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+  "cts__clock__skew__setup__pre_repair": 0.27037,
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+}