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‎docs/user/FlowVariables.md‎

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| <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
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| <a name="SYNTH_OPT_HIER"></a>SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| |
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| <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| *This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion #8080.| |
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| <a name="SYNTH_WRAPPED_ADDERS"></a>SYNTH_WRAPPED_ADDERS| Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.| |
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| <a name="SYNTH_WRAPPED_MULTIPLIERS"></a>SYNTH_WRAPPED_MULTIPLIERS| Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.| |
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| <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
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| <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| |
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| <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| |
@@ -278,6 +280,8 @@ configuration file.
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- [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
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- [SYNTH_OPT_HIER](#SYNTH_OPT_HIER)
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- [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES)
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- [SYNTH_WRAPPED_ADDERS](#SYNTH_WRAPPED_ADDERS)
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- [SYNTH_WRAPPED_MULTIPLIERS](#SYNTH_WRAPPED_MULTIPLIERS)
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- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
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- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
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- [VERILOG_DEFINES](#VERILOG_DEFINES)
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- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
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- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
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- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
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- [TNS_END_PERCENT](#TNS_END_PERCENT)
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## cts variables
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‎flow/Makefile‎

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$(2)=$(RESULTS_DIR)/$(1) $(OPENROAD_GUI_CMD) $(SCRIPTS_DIR)/open.tcl
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endef
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# Enables "make gui_5_1_grt-failed"
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$(eval $(call OPEN_GUI_SHORTCUT,5_1_grt-failed,5_1_grt-failed.odb))
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# Separate dependency checking and doing a step. This can
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# be useful to retest a stage without having to delete the
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# target, or when building a wafer thin layer on top of
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do-place:
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$(UNSET_AND_MAKE) do-3_1_place_gp_skip_io do-3_2_place_iop do-3_3_place_gp do-3_4_place_resized do-3_5_place_dp do-3_place do-3_place.sdc
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# Custom repair_timing target after placement
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$(eval $(call do-step,3_6_place_repair_timing,$(RESULTS_DIR)/3_5_place_dp.odb $(RESULTS_DIR)/3_place.sdc,repair_timing_post_place))
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.PHONY: place_repair_timing
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place_repair_timing: $(RESULTS_DIR)/3_6_place_repair_timing.odb
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# Clean Targets
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#-------------------------------------------------------------------------------
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.PHONY: clean_place

‎flow/designs/asap7/aes-block/rules-base.json‎

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"finish__timing__drv__setup_violation_count": {
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"detailedroute__timing__hold__ws": {
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"value": -22.5,
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}

‎flow/designs/asap7/aes-mbff/rules-base.json‎

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"cts__timing__hold__tns": {
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"value": -38.4,
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"globalroute__timing__setup__tns": {
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"value": -19.0,
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"detailedroute__route__wirelength": {
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"value": 74683,
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},
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"detailedroute__route__drc_errors": {
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"detailedroute__antenna_diodes_count": {
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"value": 5,
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"value": 100,
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"value": -35.3,
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"detailedroute__timing__hold__ws": {
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"detailedroute__timing__hold__tns": {
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"compare": ">="
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}

‎flow/designs/asap7/aes/rules-base.json‎

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"value": 1704,
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