@@ -11,14 +11,17 @@ export SYNTH_SDC_FILE = $(SDC_FILE)
1111
1212export PLACE_DENSITY_LB_ADDON = 0.05
1313
14- export IO_CONSTRAINTS = $(dir $(DESIGN_CONFIG ) ) /io.tcl
15- export MACRO_PLACEMENT_TCL = $(dir $(DESIGN_CONFIG ) ) /macro-placement.tcl
16-
1714export PDN_TCL = $(dir $(DESIGN_CONFIG ) ) /pdn.tcl
1815
16+ # pre set CORE and DIE to avoid MPL
17+ # add IO and MACRO pre placement
1918export CORE_AREA = 2.5 2.5 1397.5 1397.5
2019export DIE_AREA = 0 0 1400 1400
2120
21+ export IO_CONSTRAINTS = $(dir $(DESIGN_CONFIG ) ) /io.tcl
22+ export MACRO_PLACEMENT_TCL = $(dir $(DESIGN_CONFIG ) ) /macro-placement.tcl
23+
24+ # LIB and LEF files for memories and register files used
2225export BC_ADDITIONAL_LIBS += $(PLATFORM_DIR ) /lib/fakeram_256x128.lib \
2326 $(PLATFORM_DIR ) /lib/fakeram_256x64.lib \
2427 $(PLATFORM_DIR ) /lib/fakeram_32x46.lib \
@@ -40,10 +43,9 @@ export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/fakeram_256x128.lef \
4043 $(PLATFORM_DIR ) /lef/fakeregfile_128x64.lef
4144
4245
43- # export CACHED_NETLIST = $(realpath ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/MegaBoom.v)
44-
45- export SYNTH_ARGS =-noshare
46-
46+ export SYNTH_ARGS ?= -noshare
4747
48- export MIN_ROUTING_LAYER = M2
49- export MAX_ROUTING_LAYER = M9
48+ # since this will be either top level macro or chip itself, allow routing to top of the
49+ # metal stack
50+ export MIN_ROUTING_LAYER = M2
51+ export MAX_ROUTING_LAYER = M9
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