Merge pull request #2662 from Pinata-Consulting/mock-array-multiplier

Mock array multiplier

Author: maliberty

flow/designs/asap7/mock-array/Element/config.mk

@@ -8,7 +8,7 @@ export SDC_FILE               = designs/asap7/mock-array/constraints.sdc
 
 export PLATFORM               = asap7
 
-export PLACE_DENSITY          = 0.50
+export PLACE_DENSITY          = 0.82
 
 export CORE_AREA = $(shell \
   export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \

flow/designs/asap7/mock-array/metadata-base-ok.json

@@ -1,6 +1,6 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 19674.33,
+        "value": 113607.14,
         "compare": "<="
     },
     "constraints__clocks__count": {
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -32.57,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/mock-array/rules-base.json

@@ -7,3 +7,4 @@ target/
 .bloop/
 .bsp/
 test_run_dir/
+*.f

flow/designs/src/mock-array/.gitignore

@@ -24,6 +24,26 @@ module Element(
   output        io_lsbOuts_6,
   output        io_lsbOuts_7
 );
+  wire [31:0] io_outs_left_mult_a;
+  wire [31:0] io_outs_left_mult_b;
+  wire [31:0] io_outs_left_mult_o;
+  wire  io_outs_left_mult_rst;
+  wire  io_outs_left_mult_clk;
+  wire [31:0] io_outs_up_mult_a;
+  wire [31:0] io_outs_up_mult_b;
+  wire [31:0] io_outs_up_mult_o;
+  wire  io_outs_up_mult_rst;
+  wire  io_outs_up_mult_clk;
+  wire [31:0] io_outs_right_mult_a;
+  wire [31:0] io_outs_right_mult_b;
+  wire [31:0] io_outs_right_mult_o;
+  wire  io_outs_right_mult_rst;
+  wire  io_outs_right_mult_clk;
+  wire [31:0] io_outs_down_mult_a;
+  wire [31:0] io_outs_down_mult_b;
+  wire [31:0] io_outs_down_mult_o;
+  wire  io_outs_down_mult_rst;
+  wire  io_outs_down_mult_clk;
   reg [63:0] REG;
   reg [63:0] REG_1;
   reg [63:0] REG_2;
@@ -32,15 +52,43 @@ module Element(
   reg [63:0] REG_5;
   reg [63:0] REG_6;
   reg [63:0] REG_7;
-  reg [63:0] io_outs_left_REG;
-  reg [63:0] io_outs_up_REG;
-  reg [63:0] io_outs_right_REG;
-  reg [63:0] io_outs_down_REG;
+  reg [31:0] io_outs_left_REG;
+  reg [31:0] io_outs_up_REG;
+  reg [31:0] io_outs_right_REG;
+  reg [31:0] io_outs_down_REG;
   reg  REG_8;
-  assign io_outs_down = io_outs_down_REG;
-  assign io_outs_right = io_outs_right_REG;
-  assign io_outs_up = io_outs_up_REG;
-  assign io_outs_left = io_outs_left_REG;
+  multiplier io_outs_left_mult (
+    .a(io_outs_left_mult_a),
+    .b(io_outs_left_mult_b),
+    .o(io_outs_left_mult_o),
+    .rst(io_outs_left_mult_rst),
+    .clk(io_outs_left_mult_clk)
+  );
+  multiplier io_outs_up_mult (
+    .a(io_outs_up_mult_a),
+    .b(io_outs_up_mult_b),
+    .o(io_outs_up_mult_o),
+    .rst(io_outs_up_mult_rst),
+    .clk(io_outs_up_mult_clk)
+  );
+  multiplier io_outs_right_mult (
+    .a(io_outs_right_mult_a),
+    .b(io_outs_right_mult_b),
+    .o(io_outs_right_mult_o),
+    .rst(io_outs_right_mult_rst),
+    .clk(io_outs_right_mult_clk)
+  );
+  multiplier io_outs_down_mult (
+    .a(io_outs_down_mult_a),
+    .b(io_outs_down_mult_b),
+    .o(io_outs_down_mult_o),
+    .rst(io_outs_down_mult_rst),
+    .clk(io_outs_down_mult_clk)
+  );
+  assign io_outs_down = {{32'd0}, io_outs_down_REG};
+  assign io_outs_right = {{32'd0}, io_outs_right_REG};
+  assign io_outs_up = {{32'd0}, io_outs_up_REG};
+  assign io_outs_left = {{32'd0}, io_outs_left_REG};
   assign io_lsbOuts_0 = io_lsbIns_1;
   assign io_lsbOuts_1 = io_lsbIns_2;
   assign io_lsbOuts_2 = io_lsbIns_3;
@@ -49,6 +97,22 @@ module Element(
   assign io_lsbOuts_5 = io_lsbIns_6;
   assign io_lsbOuts_6 = io_lsbIns_7;
   assign io_lsbOuts_7 = io_outs_left[0];
+  assign io_outs_left_mult_a = REG[31:0];
+  assign io_outs_left_mult_b = REG_1[31:0];
+  assign io_outs_left_mult_rst = 1'h0;
+  assign io_outs_left_mult_clk = clock;
+  assign io_outs_up_mult_a = REG_2[31:0];
+  assign io_outs_up_mult_b = REG_3[31:0];
+  assign io_outs_up_mult_rst = 1'h0;
+  assign io_outs_up_mult_clk = clock;
+  assign io_outs_right_mult_a = REG_4[31:0];
+  assign io_outs_right_mult_b = REG_5[31:0];
+  assign io_outs_right_mult_rst = 1'h0;
+  assign io_outs_right_mult_clk = clock;
+  assign io_outs_down_mult_a = REG_6[31:0];
+  assign io_outs_down_mult_b = REG_7[31:0];
+  assign io_outs_down_mult_rst = 1'h0;
+  assign io_outs_down_mult_clk = clock;
   always @(posedge clock) begin
     REG <= io_ins_down;
     REG_1 <= io_ins_left;
@@ -58,10 +122,10 @@ module Element(
     REG_5 <= io_ins_right;
     REG_6 <= io_ins_left;
     REG_7 <= io_ins_up;
-    io_outs_left_REG <= REG ^ REG_1;
-    io_outs_up_REG <= REG_2 ^ REG_3;
-    io_outs_right_REG <= REG_4 ^ REG_5;
-    io_outs_down_REG <= REG_6 ^ REG_7;
+    io_outs_left_REG <= io_outs_left_mult_o;
+    io_outs_up_REG <= io_outs_up_mult_o;
+    io_outs_right_REG <= io_outs_right_mult_o;
+    io_outs_down_REG <= io_outs_down_mult_o;
     REG_8 <= io_lsbIns_4;
   end
 endmodule

flow/designs/src/mock-array/Element.v

@@ -25,3 +25,5 @@ resolvers ++= Seq(
   Resolver.sonatypeRepo("snapshots"),
   Resolver.sonatypeRepo("releases")
 )
+
+resourceDirectory in Compile := baseDirectory.value / "src/main/resources"