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malibertymaliberty
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Merge pull request #764 from Pinata-Consulting/mirrored-pins
Mirrored pins
2 parents 50d7f98 + bbfc23a commit 4ad47a4

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15 files changed

+2754
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‎flow/designs/asap7/mock-array-big/Element/config.mk‎

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export DESIGN_NAME = Element
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export DESIGN_NICKNAME = mock-array-big_Element
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export VERILOG_FILES = designs/src/mock-array-big/*.v
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export SDC_FILE = designs/asap7/mock-array-big/constraints.sdc
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export PLATFORM = asap7
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export PLACE_DENSITY = 0.40
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export CORE_UTILIZATION = 20
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export IO_CONSTRAINTS = designs/asap7/mock-array-big/Element/io.tcl

‎flow/designs/asap7/mock-array-big/Element/io.tcl‎

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proc pin1 {fmt p} {
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set result [list]
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for {set m 0} {$m < $p} {incr m} {
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lappend result [format $fmt $m]
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}
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return $result
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}
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set data_width 8
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set assignments [list \
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top bottom \
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[list [ concat \
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{*}[pin1 {io_ins_2[%d]} $data_width] \
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{*}[pin1 {io_outs_2[%d]} $data_width] \
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] \
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[ concat \
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{*}[pin1 {io_outs_0[%d]} $data_width] \
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{*}[pin1 {io_ins_0[%d]} $data_width] \
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]] \
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left right \
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[list [ concat \
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{*}[pin1 {io_ins_3[%d]} $data_width] \
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{*}[pin1 {io_outs_3[%d]} $data_width] \
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] \
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[ concat \
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{*}[pin1 {io_outs_1[%d]} $data_width] \
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{*}[pin1 {io_ins_1[%d]} $data_width] \
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]] \
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]
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proc zip {list1 list2} {
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set result {}
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set length [llength $list1]
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for {set i 0} {$i < $length} {incr i} {
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lappend result [lindex $list1 $i] [lindex $list2 $i]
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}
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return $result
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}
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foreach {direction direction2 names} $assignments {
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set mirrored [zip {*}$names]
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set_io_pin_constraint -region $direction:* -pin_names [lindex $names 0]
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set_io_pin_constraint -region $direction2:* -pin_names [lindex $names 1]
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set_io_pin_constraint -mirrored_pins $mirrored
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}

‎flow/designs/asap7/mock-array-big/config.mk‎

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export DESIGN_NAME = MockArray
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export DESIGN_NICKNAME = mock-array-big
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export VERILOG_FILES_BLACKBOX = designs/src/mock-array-big/Element.v
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export VERILOG_FILES = designs/src/mock-array-big/*.v
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export SDC_FILE = designs/asap7/mock-array-big/constraints.sdc
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export PLATFORM = asap7
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export PLACE_DENSITY = 0.30
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export CORE_UTILIZATION = 20
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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BLOCKS = Element
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export GDS_ALLOW_EMPTY = Element
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export MACRO_PLACEMENT = ./designs/asap7/mock-array-big/macro-placement.cfg
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export IO_CONSTRAINTS = designs/asap7/mock-array-big/io.tcl
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export MACRO_PLACE_HALO = 2 2

‎flow/designs/asap7/mock-array-big/constraints.sdc‎

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set sdc_version 2.0
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create_clock [get_ports clock] -period 250 -waveform {0 125}
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set clk_name clock
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set clk_port_name clock
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set clk_period 250
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/mock-array-big/io.tcl‎

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proc pin2 {fmt p q} {
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set result [list]
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for {set m 0} {$m < $p} {incr m} {
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for {set n 0} {$n < $q} {incr n} {
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lappend result [format $fmt $m $n]
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}
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}
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return $result
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}
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set data_width 8
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set rows 8
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set cols 8
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set assignments [list \
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top \
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[ concat \
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{*}[pin2 {io_insHorizontal_1_%d[%d]} $cols $data_width] \
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{*}[pin2 {io_outsHorizontal_1_%d[%d]} $cols $data_width] \
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] \
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bottom \
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[ concat \
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{*}[pin2 {io_insHorizontal_0_%d[%d]} $cols $data_width] \
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{*}[pin2 {io_outsHorizontal_0_%d[%d]} $cols $data_width] \
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] \
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left \
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[ concat \
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{*}[pin2 {io_insVertical_1_%d[%d]} $rows $data_width] \
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{*}[pin2 {io_outsVertical_1_%d[%d]} $rows $data_width] \
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] \
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right \
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[ concat \
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{*}[pin2 {io_insVertical_0_%d[%d]} $rows $data_width] \
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{*}[pin2 {io_outsVertical_0_%d[%d]} $rows $data_width] \
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] \
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]
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foreach {direction names} $assignments {
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set_io_pin_constraint -region $direction:* -pin_names $names
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}

‎flow/designs/asap7/mock-array-big/macro-placement.cfg‎

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ces_0_0 R0 10 10
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ces_0_1 R0 35 10
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ces_0_2 R0 60 10
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ces_0_3 R0 85 10
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ces_0_4 R0 110 10
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ces_0_5 R0 135 10
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ces_0_6 R0 160 10
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ces_0_7 R0 185 10
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ces_1_0 R0 10 35
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ces_1_1 R0 35 35
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ces_1_2 R0 60 35
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ces_1_3 R0 85 35
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ces_1_4 R0 110 35
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ces_1_5 R0 135 35
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ces_1_6 R0 160 35
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ces_1_7 R0 185 35
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ces_2_0 R0 10 60
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ces_2_1 R0 35 60
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ces_2_2 R0 60 60
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ces_2_3 R0 85 60
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ces_2_4 R0 110 60
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ces_2_5 R0 135 60
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ces_2_6 R0 160 60
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ces_2_7 R0 185 60
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ces_3_0 R0 10 85
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ces_3_1 R0 35 85
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ces_3_2 R0 60 85
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ces_3_3 R0 85 85
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ces_3_4 R0 110 85
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ces_3_5 R0 135 85
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ces_3_6 R0 160 85
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ces_3_7 R0 185 85
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ces_4_0 R0 10 110
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ces_4_1 R0 35 110
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ces_4_2 R0 60 110
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ces_4_3 R0 85 110
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ces_4_4 R0 110 110
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ces_4_5 R0 135 110
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ces_4_6 R0 160 110
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ces_4_7 R0 185 110
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ces_5_0 R0 10 135
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ces_5_1 R0 35 135
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ces_5_2 R0 60 135
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ces_5_3 R0 85 135
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ces_5_4 R0 110 135
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ces_5_5 R0 135 135
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ces_5_6 R0 160 135
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ces_5_7 R0 185 135
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ces_6_0 R0 10 160
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ces_6_1 R0 35 160
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ces_6_2 R0 60 160
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ces_6_3 R0 85 160
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ces_6_4 R0 110 160
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ces_6_5 R0 135 160
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ces_6_6 R0 160 160
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ces_6_7 R0 185 160
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ces_7_0 R0 10 185
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ces_7_1 R0 35 185
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ces_7_2 R0 60 185
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ces_7_3 R0 85 185
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ces_7_4 R0 110 185
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ces_7_5 R0 135 185
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ces_7_6 R0 160 185
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ces_7_7 R0 185 185

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