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malibertymaliberty
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Merge pull request #3278 from luarss/topic/add-tclint
Add tclint CI
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‎.github/workflows/github-actions-lint-tcl.yml‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
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name: Lint Tcl code
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on:
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push:
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branches:
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- master
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pull_request:
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branches:
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- master
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jobs:
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build:
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runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
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steps:
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- name: Checkout repository
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uses: actions/checkout@v4
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- name: Install Dependencies
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run: |
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python3 -m pip install -U --user tclint==0.4.2
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- name: Lint
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run: |
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tclfmt --version
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tclfmt --in-place .
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git diff --exit-code
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tclint --no-check-style .

‎flow/designs/asap7/aes-block/constraint.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
set clk_name clk
1+
set clk_name clk
22
set clk_port_name clk
33
set clk_period 475
44
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
99

1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1313
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes-mbff/constraint.sdc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
set clk_name clk
1+
set clk_name clk
22
set clk_port_name clk
3-
set clk_period 400
3+
set clk_period 400
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
99

1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes/constraint.sdc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
set clk_name clk
1+
set clk_name clk
22
set clk_port_name clk
3-
set clk_period 400
3+
set clk_period 400
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
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1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1313
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes_lvt/constraint.sdc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
set clk_name clk
1+
set clk_name clk
22
set clk_port_name clk
3-
set clk_period 400
3+
set clk_period 400
44
set clk_io_pct 0.2
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66
set clk_port [get_ports $clk_port_name]
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
99

1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1313
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/ethmac/constraint.sdc‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,28 +4,28 @@ set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
66
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
7+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
88
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
99

1010
set tx_clk_name mtx_clk_pad_i
1111
set tx_clk_port [get_ports $tx_clk_name]
1212
set tx_clk_period 300
1313
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
1414
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
15+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
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set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
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1818
set rx_clk_name mrx_clk_pad_i
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set rx_clk_port [get_ports $rx_clk_name]
2020
set rx_clk_period 300
2121
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
2222
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
23+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
2424
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
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2626
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
27+
-group [get_clocks $top_clk_name] \
28+
-group [get_clocks $tx_clk_name] \
29+
-group [get_clocks $rx_clk_name]
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3131
set_max_fanout 10 [current_design]

‎flow/designs/asap7/ethmac_lvt/constraint.sdc‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,26 +4,26 @@ set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
66
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
7+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
88
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
99

1010
set tx_clk_name mtx_clk_pad_i
1111
set tx_clk_port [get_ports $tx_clk_name]
1212
set tx_clk_period 300
1313
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
1414
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
15+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
1616
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
1717

1818
set rx_clk_name mrx_clk_pad_i
1919
set rx_clk_port [get_ports $rx_clk_name]
2020
set rx_clk_period 300
2121
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
2222
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
23+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
2424
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
2525

2626
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
27+
-group [get_clocks $top_clk_name] \
28+
-group [get_clocks $tx_clk_name] \
29+
-group [get_clocks $rx_clk_name]

‎flow/designs/asap7/gcd/constraint.sdc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11
current_design gcd
22

3-
set clk_name core_clock
3+
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 310
5+
set clk_period 310
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]
99

10-
create_clock -name $clk_name -period $clk_period $clk_port
10+
create_clock -name $clk_name -period $clk_period $clk_port
1111

1212
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1313

14-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
14+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1515
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/ibex/constraint.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
set clk_name core_clock
1+
set clk_name core_clock
22
set clk_port_name clk_i
33
set clk_period 1260
44
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
99

1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1313
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/ibex/constraint_pos_slack.sdc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
set clk_name core_clock
1+
set clk_name core_clock
22
set clk_port_name clk_i
33
set clk_period 1468
44
set clk_io_pct 0.2
@@ -9,5 +9,5 @@ create_clock -name $clk_name -period $clk_period $clk_port
99

1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
1313
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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