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1 parent 6fc3358 commit 4d1fe73Copy full SHA for 4d1fe73
flow/designs/asap7/mock-array-big/Element/pdn.tcl
@@ -11,8 +11,13 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
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####################################
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# standard cell grid
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+# M1 M2 are for follow pin, width derived from PG rail in standard cell
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+# M5 stripe width rerived from one of width allowed in LEF, offset and pitch
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+# put stripe on M5 track
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+# M4 M5 ring follow stripe width
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define_pdn_grid -name {top} -voltage_domains {CORE}
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+
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add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084}
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add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
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