rapidus2hp: add FLOW_VARIANT for verific

Signed-off-by: Vitor Bandeira <[email protected]>

Author: vvbandeira

flow/designs/rapidus2hp/cva6/config.mk

@@ -2,6 +2,10 @@ export PLATFORM               = rapidus2hp
 
 export DESIGN_NAME            = cva6
 
+ifeq ($(FLOW_VARIANT), verific)
+	export SYNTH_HDL_FRONTEND = verific
+endif
+
 # Some files are listed specifically vs. sorted wilcard to control the order (makes Verific happy)
 export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)
 export VERILOG_FILES          = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \

flow/designs/rapidus2hp/ethmac/config.mk

@@ -2,6 +2,10 @@ export PLATFORM               = rapidus2hp
 
 export DESIGN_NAME            = ethmac
 
+ifeq ($(FLOW_VARIANT), verific)
+	export SYNTH_HDL_FRONTEND = verific
+endif
+
 export VERILOG_FILES         = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
 export SDC_FILE              = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ABC_AREA               = 1

flow/designs/rapidus2hp/gcd/config.mk

@@ -2,6 +2,10 @@ export DESIGN_NICKNAME = gcd
 export DESIGN_NAME = gcd
 export PLATFORM    = rapidus2hp
 
+ifeq ($(FLOW_VARIANT), verific)
+	export SYNTH_HDL_FRONTEND = verific
+endif
+
 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 

flow/designs/rapidus2hp/hercules_idecode/config.mk

@@ -2,6 +2,10 @@ export PLATFORM             = rapidus2hp
 
 export DESIGN_NAME          = hercules_idecode
 
+ifeq ($(FLOW_VARIANT), verific)
+  export SYNTH_HDL_FRONTEND = verific
+endif
+
 export SRC_HOME             = /platforms/Rapidus/designs/hercules_idecode
 export VERILOG_FILES        = $(sort $(wildcard $(SRC_HOME)/hercules_idecode/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \

flow/designs/rapidus2hp/hercules_is_int/config.mk

@@ -8,6 +8,10 @@ ifeq ($(FLOW_VARIANT), gatelevel)
   export SYNTH_NETLIST_FILES  = $(SRC_HOME)/ca78_8t_postroute_0707.v
 endif
 
+ifeq ($(FLOW_VARIANT), verific)
+	export SYNTH_HDL_FRONTEND = verific
+endif
+
 export VERILOG_FILES          = $(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv))

flow/designs/rapidus2hp/ibex/config.mk

@@ -3,6 +3,10 @@ export PLATFORM               = rapidus2hp
 export DESIGN_NICKNAME        = ibex
 export DESIGN_NAME            = ibex_core
 
+ifeq ($(FLOW_VARIANT), verific)
+	export SYNTH_HDL_FRONTEND = verific
+endif
+
 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
     $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
 

flow/designs/rapidus2hp/jpeg/config.mk

@@ -3,6 +3,10 @@ export PLATFORM               = rapidus2hp
 export DESIGN_NAME            = jpeg_encoder
 export DESIGN_NICKNAME        = jpeg
 
+ifeq ($(FLOW_VARIANT), verific)
+	export SYNTH_HDL_FRONTEND = verific
+endif
+
 export VERILOG_FILES          = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
 export VERILOG_INCLUDE_DIRS   = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc