Aligned clock period with July 2025 demo

tclfmt fix + added opt constraint SDC

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

flow/designs/rapidus2hp/cva6/autotuner.json

@@ -4,15 +4,23 @@
         "type": "float",
         "minmax": [
             990,
-            1015
+            1250
         ],
         "step": 0
     },
     "CORE_UTILIZATION": {
+        "type": "int",
+        "minmax": [
+            40,
+            60
+        ],
+        "step": 1
+    },
+    "CTS_BUF_DISTANCE": {
         "type": "int",
         "minmax": [
             25,
-            45
+            50
         ],
         "step": 1
     },

flow/designs/rapidus2hp/cva6/constraint.sdc

@@ -3,9 +3,7 @@
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
-set clk_period 1000
+set clk_period 1380
 set input_delay 0.46
 set output_delay 0.11
 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
-
-set_false_path -to [get_ports {rvfi_probes_o}]

flow/designs/rapidus2hp/cva6/opt_constraint.sdc

@@ -0,0 +1,9 @@
+# Derived from cva6_synth.tcl and Makefiles
+
+set clk_name main_clk
+set clk_port clk_i
+set clk_ports_list [list $clk_port]
+set clk_period 1013.87619516354
+set input_delay 0.46
+set output_delay 0.11
+create_clock [get_ports $clk_port] -name $clk_name -period $clk_period