Skip to content

Commit 5136d2b

Browse files
committed
update private ci metrics for tns5
intel16/aes [INFO] Tightening rule synth__design__instance__area__stdcell from 7642 to 7641.73. [INFO] Updating failing rule cts__design__instance__count__setup_buffer from 1034 to 1186. [INFO] Tightening rule globalroute__timing__clock__slack from -419.99 to -419.5. [INFO] Tightening rule globalroute__timing__setup__ws from -419.99 to -419.5. intel22/ibex [INFO] Updating failing rule cts__design__instance__count__setup_buffer from 900 to 994. [INFO] Tightening rule finish__timing__setup__ws from -495.71 to -382.31. [INFO] Tightening rule finish__timing__wns_percent_delay from -22.11 to -17.17. Signed-off-by: Matt Liberty <[email protected]>
1 parent 4a55eb2 commit 5136d2b

File tree

4 files changed

+178
-260
lines changed

4 files changed

+178
-260
lines changed

flow/designs/intel16/aes/metadata-base-ok.json

Lines changed: 84 additions & 124 deletions
Original file line numberDiff line numberDiff line change
@@ -15,52 +15,40 @@
1515
"cts__design__die__area": 62500,
1616
"cts__design__die__area__post_repair": 62500,
1717
"cts__design__die__area__pre_repair": 62500,
18-
"cts__design__instance__area": 11328.8,
18+
"cts__design__instance__area": 11471.1,
1919
"cts__design__instance__area__macros": 0,
2020
"cts__design__instance__area__macros__post_repair": 0,
2121
"cts__design__instance__area__macros__pre_repair": 0,
2222
"cts__design__instance__area__post_repair": 10583.9,
2323
"cts__design__instance__area__pre_repair": 10583.9,
24-
"cts__design__instance__area__stdcell": 11328.8,
24+
"cts__design__instance__area__stdcell": 11471.1,
2525
"cts__design__instance__area__stdcell__post_repair": 10583.9,
2626
"cts__design__instance__area__stdcell__pre_repair": 10583.9,
27-
"cts__design__instance__count": 18352,
27+
"cts__design__instance__count": 18469,
2828
"cts__design__instance__count__hold_buffer": 535.0,
2929
"cts__design__instance__count__macros": 0,
3030
"cts__design__instance__count__macros__post_repair": 0,
3131
"cts__design__instance__count__macros__pre_repair": 0,
3232
"cts__design__instance__count__post_repair": 16856,
3333
"cts__design__instance__count__pre_repair": 16856,
34-
"cts__design__instance__count__setup_buffer": 961.0,
35-
"cts__design__instance__count__stdcell": 18352,
34+
"cts__design__instance__count__setup_buffer": 1078.0,
35+
"cts__design__instance__count__stdcell": 18469,
3636
"cts__design__instance__count__stdcell__post_repair": 16856,
3737
"cts__design__instance__count__stdcell__pre_repair": 16856,
3838
"cts__design__instance__displacement__max": 6.48,
39-
"cts__design__instance__displacement__mean": 0.1065,
40-
"cts__design__instance__displacement__total": 2129.68,
41-
"cts__design__instance__utilization": 0.186921,
39+
"cts__design__instance__displacement__mean": 0.1125,
40+
"cts__design__instance__displacement__total": 2259.26,
41+
"cts__design__instance__utilization": 0.189269,
4242
"cts__design__instance__utilization__post_repair": 0.17463,
4343
"cts__design__instance__utilization__pre_repair": 0.17463,
44-
"cts__design__instance__utilization__stdcell": 0.186921,
44+
"cts__design__instance__utilization__stdcell": 0.189269,
4545
"cts__design__instance__utilization__stdcell__post_repair": 0.17463,
4646
"cts__design__instance__utilization__stdcell__pre_repair": 0.17463,
4747
"cts__design__io": 388,
4848
"cts__design__io__post_repair": 388,
4949
"cts__design__io__pre_repair": 388,
5050
"cts__design__violations": 0,
51-
"cts__power__internal__total": 0.00404127,
52-
"cts__power__internal__total__post_repair": 0.00392691,
53-
"cts__power__internal__total__pre_repair": 0.00392691,
54-
"cts__power__leakage__total": 1.41037e-08,
55-
"cts__power__leakage__total__post_repair": 1.31343e-08,
56-
"cts__power__leakage__total__pre_repair": 1.31343e-08,
57-
"cts__power__switching__total": 0.00465414,
58-
"cts__power__switching__total__post_repair": 0.00475504,
59-
"cts__power__switching__total__pre_repair": 0.00475504,
60-
"cts__power__total": 0.00869543,
61-
"cts__power__total__post_repair": 0.00868197,
62-
"cts__power__total__pre_repair": 0.00868197,
63-
"cts__route__wirelength__estimated": 260387,
51+
"cts__route__wirelength__estimated": 264209,
6452
"cts__timing__drv__hold_violation_count": 0,
6553
"cts__timing__drv__hold_violation_count__post_repair": 273,
6654
"cts__timing__drv__hold_violation_count__pre_repair": 273,
@@ -82,16 +70,16 @@
8270
"cts__timing__drv__max_slew_limit": 0.153056,
8371
"cts__timing__drv__max_slew_limit__post_repair": 0.159357,
8472
"cts__timing__drv__max_slew_limit__pre_repair": 0.159357,
85-
"cts__timing__drv__setup_violation_count": 145,
73+
"cts__timing__drv__setup_violation_count": 114,
8674
"cts__timing__drv__setup_violation_count__post_repair": 387,
8775
"cts__timing__drv__setup_violation_count__pre_repair": 387,
88-
"cts__timing__setup__tns": -12439.1,
76+
"cts__timing__setup__tns": -7554.59,
8977
"cts__timing__setup__tns__post_repair": -295651,
9078
"cts__timing__setup__tns__pre_repair": -295651,
9179
"cts__timing__setup__ws": -169.677,
9280
"cts__timing__setup__ws__post_repair": -1400.58,
9381
"cts__timing__setup__ws__pre_repair": -1400.58,
94-
"detailedplace__cpu__total": 17.19,
82+
"detailedplace__cpu__total": 15.18,
9583
"detailedplace__design__core__area": 60607.3,
9684
"detailedplace__design__die__area": 62500,
9785
"detailedplace__design__instance__area": 10571.7,
@@ -107,13 +95,9 @@
10795
"detailedplace__design__instance__utilization__stdcell": 0.17443,
10896
"detailedplace__design__io": 388,
10997
"detailedplace__design__violations": 0,
110-
"detailedplace__mem__peak": 356368.0,
111-
"detailedplace__power__internal__total": 0.00390845,
112-
"detailedplace__power__leakage__total": 1.31114e-08,
113-
"detailedplace__power__switching__total": 0.00456661,
114-
"detailedplace__power__total": 0.00847507,
98+
"detailedplace__mem__peak": 352300.0,
11599
"detailedplace__route__wirelength__estimated": 264814,
116-
"detailedplace__runtime__total": "0:17.52",
100+
"detailedplace__runtime__total": "0:15.52",
117101
"detailedplace__timing__drv__hold_violation_count": 0,
118102
"detailedplace__timing__drv__max_cap": 0,
119103
"detailedplace__timing__drv__max_cap_limit": 0.189783,
@@ -125,66 +109,62 @@
125109
"detailedplace__timing__setup__tns": -276334,
126110
"detailedplace__timing__setup__ws": -1305.21,
127111
"detailedroute__route__drc_errors": 0,
128-
"detailedroute__route__drc_errors__iter:1": 18377,
129-
"detailedroute__route__drc_errors__iter:10": 1,
112+
"detailedroute__route__drc_errors__iter:1": 17325,
113+
"detailedroute__route__drc_errors__iter:10": 3,
130114
"detailedroute__route__drc_errors__iter:11": 0,
131-
"detailedroute__route__drc_errors__iter:2": 3285,
132-
"detailedroute__route__drc_errors__iter:3": 2428,
133-
"detailedroute__route__drc_errors__iter:4": 374,
134-
"detailedroute__route__drc_errors__iter:5": 150,
135-
"detailedroute__route__drc_errors__iter:6": 77,
136-
"detailedroute__route__drc_errors__iter:7": 51,
137-
"detailedroute__route__drc_errors__iter:8": 36,
138-
"detailedroute__route__drc_errors__iter:9": 11,
139-
"detailedroute__route__net": 18611,
115+
"detailedroute__route__drc_errors__iter:2": 2674,
116+
"detailedroute__route__drc_errors__iter:3": 1881,
117+
"detailedroute__route__drc_errors__iter:4": 283,
118+
"detailedroute__route__drc_errors__iter:5": 91,
119+
"detailedroute__route__drc_errors__iter:6": 37,
120+
"detailedroute__route__drc_errors__iter:7": 13,
121+
"detailedroute__route__drc_errors__iter:8": 6,
122+
"detailedroute__route__drc_errors__iter:9": 3,
123+
"detailedroute__route__net": 18728,
140124
"detailedroute__route__net__special": 2,
141-
"detailedroute__route__vias": 201707,
125+
"detailedroute__route__vias": 203121,
142126
"detailedroute__route__vias__multicut": 0,
143-
"detailedroute__route__vias__singlecut": 201707,
144-
"detailedroute__route__wirelength": 335692,
145-
"detailedroute__route__wirelength__iter:1": 337358,
146-
"detailedroute__route__wirelength__iter:10": 335693,
147-
"detailedroute__route__wirelength__iter:11": 335692,
148-
"detailedroute__route__wirelength__iter:2": 336358,
149-
"detailedroute__route__wirelength__iter:3": 335628,
150-
"detailedroute__route__wirelength__iter:4": 335680,
151-
"detailedroute__route__wirelength__iter:5": 335674,
152-
"detailedroute__route__wirelength__iter:6": 335665,
153-
"detailedroute__route__wirelength__iter:7": 335686,
154-
"detailedroute__route__wirelength__iter:8": 335696,
155-
"detailedroute__route__wirelength__iter:9": 335699,
156-
"finish__clock__skew__hold": 104.649,
157-
"finish__clock__skew__setup": 104.25,
158-
"finish__cpu__total": 35.68,
127+
"detailedroute__route__vias__singlecut": 203121,
128+
"detailedroute__route__wirelength": 339654,
129+
"detailedroute__route__wirelength__iter:1": 340960,
130+
"detailedroute__route__wirelength__iter:10": 339656,
131+
"detailedroute__route__wirelength__iter:11": 339654,
132+
"detailedroute__route__wirelength__iter:2": 340245,
133+
"detailedroute__route__wirelength__iter:3": 339618,
134+
"detailedroute__route__wirelength__iter:4": 339634,
135+
"detailedroute__route__wirelength__iter:5": 339651,
136+
"detailedroute__route__wirelength__iter:6": 339653,
137+
"detailedroute__route__wirelength__iter:7": 339655,
138+
"detailedroute__route__wirelength__iter:8": 339649,
139+
"detailedroute__route__wirelength__iter:9": 339655,
140+
"finish__clock__skew__hold": 113.16,
141+
"finish__clock__skew__setup": 112.762,
142+
"finish__cpu__total": 32.61,
159143
"finish__design__core__area": 60607.3,
160144
"finish__design__die__area": 62500,
161-
"finish__design__instance__area": 11328.8,
145+
"finish__design__instance__area": 11471.1,
162146
"finish__design__instance__area__macros": 0,
163-
"finish__design__instance__area__stdcell": 11328.8,
164-
"finish__design__instance__count": 18352,
147+
"finish__design__instance__area__stdcell": 11471.1,
148+
"finish__design__instance__count": 18469,
165149
"finish__design__instance__count__macros": 0,
166-
"finish__design__instance__count__stdcell": 18352,
167-
"finish__design__instance__utilization": 0.186921,
168-
"finish__design__instance__utilization__stdcell": 0.186921,
150+
"finish__design__instance__count__stdcell": 18469,
151+
"finish__design__instance__utilization": 0.189269,
152+
"finish__design__instance__utilization__stdcell": 0.189269,
169153
"finish__design__io": 388,
170-
"finish__mem__peak": 904144.0,
171-
"finish__power__internal__total": 0.00419689,
172-
"finish__power__leakage__total": 1.41037e-08,
173-
"finish__power__switching__total": 0.00416594,
174-
"finish__power__total": 0.00836284,
175-
"finish__runtime__total": "0:37.75",
154+
"finish__mem__peak": 725804.0,
155+
"finish__runtime__total": "0:39.82",
176156
"finish__timing__drv__hold_violation_count": 0.0,
177157
"finish__timing__drv__max_cap": 0,
178-
"finish__timing__drv__max_cap_limit": 0.932798,
158+
"finish__timing__drv__max_cap_limit": 0.923894,
179159
"finish__timing__drv__max_fanout": 0,
180160
"finish__timing__drv__max_fanout_limit": 1e+30,
181161
"finish__timing__drv__max_slew": 0,
182-
"finish__timing__drv__max_slew_limit": 0.716986,
162+
"finish__timing__drv__max_slew_limit": 0.708727,
183163
"finish__timing__drv__setup_violation_count": 0.0,
184164
"finish__timing__setup__tns": 0,
185-
"finish__timing__setup__ws": 70.2518,
186-
"finish__timing__wns_percent_delay": 2.74316,
187-
"floorplan__cpu__total": 2.22,
165+
"finish__timing__setup__ws": 67.8277,
166+
"finish__timing__wns_percent_delay": 2.709899,
167+
"floorplan__cpu__total": 1.98,
188168
"floorplan__design__core__area": 60607.3,
189169
"floorplan__design__die__area": 62500,
190170
"floorplan__design__instance__area": 6095.78,
@@ -196,15 +176,11 @@
196176
"floorplan__design__instance__utilization": 0.100578,
197177
"floorplan__design__instance__utilization__stdcell": 0.100578,
198178
"floorplan__design__io": 388,
199-
"floorplan__mem__peak": 219632.0,
200-
"floorplan__power__internal__total": 0.00175487,
201-
"floorplan__power__leakage__total": 4.61227e-09,
202-
"floorplan__power__switching__total": 0.000867891,
203-
"floorplan__power__total": 0.00262277,
204-
"floorplan__runtime__total": "0:02.44",
179+
"floorplan__mem__peak": 223760.0,
180+
"floorplan__runtime__total": "0:02.12",
205181
"floorplan__timing__setup__tns": -353327,
206182
"floorplan__timing__setup__ws": -1704.6,
207-
"globalplace__cpu__total": 23.22,
183+
"globalplace__cpu__total": 20.02,
208184
"globalplace__design__core__area": 60607.3,
209185
"globalplace__design__die__area": 62500,
210186
"globalplace__design__instance__area": 6095.78,
@@ -216,45 +192,37 @@
216192
"globalplace__design__instance__utilization": 0.100578,
217193
"globalplace__design__instance__utilization__stdcell": 0.100578,
218194
"globalplace__design__io": 388,
219-
"globalplace__mem__peak": 375644.0,
220-
"globalplace__power__internal__total": 0.00172428,
221-
"globalplace__power__leakage__total": 4.61227e-09,
222-
"globalplace__power__switching__total": 0.0035815,
223-
"globalplace__power__total": 0.00530578,
224-
"globalplace__runtime__total": "0:23.64",
195+
"globalplace__mem__peak": 373784.0,
196+
"globalplace__runtime__total": "0:20.37",
225197
"globalplace__timing__setup__tns": -2933240.0,
226198
"globalplace__timing__setup__ws": -13808.5,
227199
"globalroute__antenna__violating__nets": 0,
228200
"globalroute__antenna__violating__pins": 0,
229-
"globalroute__clock__skew__hold": 154.077,
230-
"globalroute__clock__skew__setup": 154.077,
201+
"globalroute__clock__skew__hold": 154.076,
202+
"globalroute__clock__skew__setup": 154.076,
231203
"globalroute__design__core__area": 60607.3,
232204
"globalroute__design__die__area": 62500,
233-
"globalroute__design__instance__area": 11328.8,
205+
"globalroute__design__instance__area": 11471.1,
234206
"globalroute__design__instance__area__macros": 0,
235-
"globalroute__design__instance__area__stdcell": 11328.8,
236-
"globalroute__design__instance__count": 18352,
207+
"globalroute__design__instance__area__stdcell": 11471.1,
208+
"globalroute__design__instance__count": 18469,
237209
"globalroute__design__instance__count__macros": 0,
238-
"globalroute__design__instance__count__stdcell": 18352,
239-
"globalroute__design__instance__utilization": 0.186921,
240-
"globalroute__design__instance__utilization__stdcell": 0.186921,
210+
"globalroute__design__instance__count__stdcell": 18469,
211+
"globalroute__design__instance__utilization": 0.189269,
212+
"globalroute__design__instance__utilization__stdcell": 0.189269,
241213
"globalroute__design__io": 388,
242-
"globalroute__power__internal__total": 0.0041791,
243-
"globalroute__power__leakage__total": 1.41037e-08,
244-
"globalroute__power__switching__total": 0.00520802,
245-
"globalroute__power__total": 0.00938713,
246-
"globalroute__timing__clock__slack": -314.999,
214+
"globalroute__timing__clock__slack": -314.505,
247215
"globalroute__timing__drv__hold_violation_count": 2,
248216
"globalroute__timing__drv__max_cap": 0,
249217
"globalroute__timing__drv__max_cap_limit": 0.172773,
250218
"globalroute__timing__drv__max_fanout": 0,
251219
"globalroute__timing__drv__max_fanout_limit": 1e+30,
252220
"globalroute__timing__drv__max_slew": 0,
253221
"globalroute__timing__drv__max_slew_limit": 0.14108,
254-
"globalroute__timing__drv__setup_violation_count": 196,
255-
"globalroute__timing__setup__tns": -31898.5,
256-
"globalroute__timing__setup__ws": -314.999,
257-
"placeopt__cpu__total": 23.22,
222+
"globalroute__timing__drv__setup_violation_count": 193,
223+
"globalroute__timing__setup__tns": -25814.2,
224+
"globalroute__timing__setup__ws": -314.505,
225+
"placeopt__cpu__total": 20.02,
258226
"placeopt__design__core__area": 60607.3,
259227
"placeopt__design__core__area__pre_opt": 60607.3,
260228
"placeopt__design__die__area": 62500,
@@ -277,16 +245,8 @@
277245
"placeopt__design__instance__utilization__stdcell__pre_opt": 0.100578,
278246
"placeopt__design__io": 388,
279247
"placeopt__design__io__pre_opt": 388,
280-
"placeopt__mem__peak": 375644.0,
281-
"placeopt__power__internal__total": 0.00362134,
282-
"placeopt__power__internal__total__pre_opt": 0.00172428,
283-
"placeopt__power__leakage__total": 1.31114e-08,
284-
"placeopt__power__leakage__total__pre_opt": 4.61227e-09,
285-
"placeopt__power__switching__total": 0.0040405,
286-
"placeopt__power__switching__total__pre_opt": 0.0035815,
287-
"placeopt__power__total": 0.00766185,
288-
"placeopt__power__total__pre_opt": 0.00530578,
289-
"placeopt__runtime__total": "0:23.64",
248+
"placeopt__mem__peak": 373784.0,
249+
"placeopt__runtime__total": "0:20.37",
290250
"placeopt__timing__drv__hold_violation_count": 0,
291251
"placeopt__timing__drv__max_cap": 0,
292252
"placeopt__timing__drv__max_cap_limit": 0.172432,
@@ -300,10 +260,10 @@
300260
"placeopt__timing__setup__ws": -1313.95,
301261
"placeopt__timing__setup__ws__pre_opt": -13808.5,
302262
"run__flow__design": "aes",
303-
"run__flow__generate_date": "2023-01-20 13:21",
263+
"run__flow__generate_date": "2023-05-04 02:49",
304264
"run__flow__metrics_version": "Metrics_2.1.2",
305265
"run__flow__openroad_commit": "N/A",
306-
"run__flow__openroad_version": "v2.0-6565-g7d2bade83",
266+
"run__flow__openroad_version": "v2.0-8031-g0051f510c",
307267
"run__flow__platform": "intel16",
308268
"run__flow__platform__capacitance_units": "1fF",
309269
"run__flow__platform__current_units": "1mA",
@@ -313,13 +273,13 @@
313273
"run__flow__platform__time_units": "1ps",
314274
"run__flow__platform__voltage_units": "1v",
315275
"run__flow__platform_commit": "cf698eea9b085cd081ae71da8f9aacc37d435813",
316-
"run__flow__scripts_commit": "17d6d54f0bf6f520a9e6a7a6d576f587c6742c79",
317-
"run__flow__uuid": "f2716547-6f1d-4cd4-b6e1-5845e5fb5a72",
276+
"run__flow__scripts_commit": "4a55eb2a35456f5495027725e33a6e7bab7e65c0",
277+
"run__flow__uuid": "ea1fe8d8-3a1e-4a26-9e83-3af6eaace346",
318278
"run__flow__variant": "base",
319-
"synth__cpu__total": 92.59,
279+
"synth__cpu__total": 84.01,
320280
"synth__design__instance__area__stdcell": 6644.9808,
321281
"synth__design__instance__count__stdcell": 17657.0,
322-
"synth__mem__peak": 719896.0,
323-
"synth__runtime__total": "1:35.99",
324-
"total_time": "0:03:20.980000"
282+
"synth__mem__peak": 725192.0,
283+
"synth__runtime__total": "1:26.59",
284+
"total_time": "0:03:04.790000"
325285
}

flow/designs/intel16/aes/rules-base.json

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 7642,
3+
"value": 7641.73,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {
@@ -32,19 +32,19 @@
3232
"compare": ">="
3333
},
3434
"cts__design__instance__count__setup_buffer": {
35-
"value": 1034,
35+
"value": 1186,
3636
"compare": "<="
3737
},
3838
"cts__design__instance__count__hold_buffer": {
3939
"value": 842,
4040
"compare": "<="
4141
},
4242
"globalroute__timing__clock__slack": {
43-
"value": -419.99,
43+
"value": -419.5,
4444
"compare": ">="
4545
},
4646
"globalroute__timing__setup__ws": {
47-
"value": -419.99,
47+
"value": -419.5,
4848
"compare": ">="
4949
},
5050
"detailedroute__route__wirelength": {

0 commit comments

Comments
 (0)