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Merge pull request #3310 from The-OpenROAD-Project-staging/add-design-configs-rapidus
added design configs for rapidus2hp platform
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‎flow/designs/rapidus2hp/README.md‎

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# Rapidus Environment Setup
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## Clone Rapidus Repo from Private GH
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The ORFS-specific files for the Rapidus platform are stored separately in the private rapidus repo. Clone out the repo into a separate directory and then set PLATFORM_HOME to point to it:
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```
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cd rapidus_platform_dir_goes_here
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git clone http://github.com/The-OpenROAD-Project-private/rapidus
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export PLATFORM_HOME=`pwd`/rapidus_platform_dir_goes_here
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```
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For more information, check out (http://github.com/The-OpenROAD-Project-private/rapidus)
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‎flow/designs/rapidus2hp/cva6/autotuner.json‎

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{
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"_SDC_FILE_PATH": "constraint.sdc",
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"_SDC_CLK_PERIOD": {
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"type": "float",
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"minmax": [
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990,
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1015
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],
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"step": 0
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},
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"CORE_UTILIZATION": {
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"type": "int",
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"minmax": [
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25,
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45
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],
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"step": 1
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},
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"CTS_CLUSTER_SIZE": {
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"type": "int",
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"minmax": [
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30,
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60
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],
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"step": 1
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},
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"CTS_CLUSTER_DIAMETER": {
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"type": "int",
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"minmax": [
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15,
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25
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],
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"step": 1
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},
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"CORE_MARGIN": {
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"type": "float",
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"minmax": [
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1.8,
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2.1
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],
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"step": 0
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}
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}

‎flow/designs/rapidus2hp/cva6/config.mk‎

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export PLATFORM = rapidus2hp
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export DESIGN_NAME = cva6
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# Some files are listed specifically vs. sorted wilcard to control the order (makes Verific happy)
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export SRC_HOME = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)
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export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/*.sv)) \
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$(SRC_HOME)/core/include/config_pkg.sv \
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$(SRC_HOME)/core/include/cv32a65x_config_pkg.sv \
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$(SRC_HOME)/core/include/riscv_pkg.sv \
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$(SRC_HOME)/core/include/ariane_pkg.sv \
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$(SRC_HOME)/core/include/build_config_pkg.sv \
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$(SRC_HOME)/core/include/std_cache_pkg.sv \
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$(SRC_HOME)/core/include/wt_cache_pkg.sv \
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$(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/common_cells/src/*.sv)) \
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$(SRC_HOME)/core/cvfpu/src/fpnew_pkg.sv \
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$(sort $(wildcard $(SRC_HOME)/vendor/pulp-platform/axi/src/*.sv)) \
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$(SRC_HOME)/core/cvfpu/src/fpnew_cast_multi.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_classifier.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_fma.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_fma_multi.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_noncomp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_block.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_rounding.sv \
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$(SRC_HOME)/core/cvfpu/src/fpnew_top.sv \
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$(sort $(wildcard $(SRC_HOME)/core/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/pmp/src/*.sv)) \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \
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$(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cache_subsystem/hpdcache/rtl/src/utils/*.sv)) \
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$(sort $(wildcard $(SRC_HOME)/core/cva6_mmu/*.sv)) \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \
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$(SRC_HOME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \
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$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
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$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
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$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
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$(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim.sv \
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$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
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$(PLATFORM_DIR)/ram/verilog/fakeram7_128x64_shim.sv \
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$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
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$(PLATFORM_DIR)/ram/verilog/fakeram7_64x28_shim.sv \
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$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
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$(PLATFORM_DIR)/ram/verilog/fakeram7_64x25_shim.sv \
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$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv
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export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include
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export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
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$(PLATFORM_DIR)/ram/lef/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
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$(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
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$(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef
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export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
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$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
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$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
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$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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# Must be defined before the ifeq's
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export SYNTH_HDL_FRONTEND = slang
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export SYNTH_HIERARCHICAL ?= 0
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ifeq ($(SYNTH_HDL_FRONTEND),verific)
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# Reduce utilization for verific since it runs into issues with DPL not being
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# able to place instances or with one-site gap/overlap issues
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export CORE_UTILIZATION = 35
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else
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ifeq ($(SYNTH_HIERARCHICAL),1)
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# Reduce the amount of resizing done between GPL and DPL
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export EARLY_SIZING_CAP_RATIO = 6
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endif
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export CORE_UTILIZATION = 45
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endif
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export CORE_MARGIN = 2
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export MACRO_PLACE_HALO = 2 2
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export PLACE_DENSITY = 0.65
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export ENABLE_DPO = 0
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# a smoketest for this option, there are a
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# few last gasp iterations
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export SKIP_LAST_GASP ?= 1
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# For use with SYNTH_HIERARCHICAL
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export SYNTH_MINIMUM_KEEP_SIZE ?= 40000

‎flow/designs/rapidus2hp/cva6/constraint.sdc‎

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# Derived from cva6_synth.tcl and Makefiles
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set clk_name main_clk
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set clk_port clk_i
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set clk_ports_list [list $clk_port]
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set clk_period 1000
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set input_delay 0.46
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set output_delay 0.11
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create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
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set_false_path -to [get_ports {rvfi_probes_o}]

‎flow/designs/rapidus2hp/ethmac/config.mk‎

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export PLATFORM = rapidus2hp
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export DESIGN_NAME = ethmac
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export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export ABC_AREA = 1
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export CORE_UTILIZATION = 45
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 0.75
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export PLACE_DENSITY = 0.70

‎flow/designs/rapidus2hp/ethmac/constraint.sdc‎

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set top_clk_name wb_clk_i
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set clk_period 875
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set clk_io_pct 0.2
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set clk_port [get_ports $top_clk_name]
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create_clock -name $top_clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
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set tx_clk_name mtx_clk_pad_i
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set tx_clk_port [get_ports $tx_clk_name]
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set tx_clk_period 300
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create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
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set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
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set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
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set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
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set rx_clk_name mrx_clk_pad_i
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set rx_clk_port [get_ports $rx_clk_name]
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set rx_clk_period 300
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create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
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set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
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set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
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set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
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set_clock_groups -name core_clock -logically_exclusive \
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-group [get_clocks $top_clk_name] \
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-group [get_clocks $tx_clk_name] \
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-group [get_clocks $rx_clk_name]
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set_max_fanout 10 [current_design]

‎flow/designs/rapidus2hp/gcd/autotuner.json‎

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{
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"_SDC_FILE_PATH": "constraint.sdc",
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"_SDC_CLK_PERIOD": {
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"type": "float",
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"minmax": [
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180,
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300
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],
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"step": 0
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},
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"CORE_UTILIZATION": {
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"type": "float",
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"minmax": [
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21,
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60
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],
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"step": 0
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},
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"CTS_CLUSTER_SIZE": {
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"type": "int",
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"minmax": [
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10,
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200
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],
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"step": 1
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},
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"CTS_CLUSTER_DIAMETER": {
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"type": "int",
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"minmax": [
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20,
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400
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],
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"step": 1
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}
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}

‎flow/designs/rapidus2hp/gcd/config.mk‎

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export DESIGN_NICKNAME = gcd
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export DESIGN_NAME = gcd
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export PLATFORM = rapidus2hp
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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export CORE_UTILIZATION = 30
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export CORE_MARGIN = .75
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export PLACE_DENSITY = 0.42

‎flow/designs/rapidus2hp/gcd/constraint.sdc‎

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current_design gcd
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set clk_name core_clock
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set clk_port_name clk
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set clk_period 185
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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