update density for failing design

Signed-off-by: Eder Monteiro <[email protected]>

Author: eder-matheus

flow/designs/ihp-sg13g2/jpeg/config.mk

@@ -6,8 +6,8 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*
 export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
-export CORE_UTILIZATION = 55
-export PLACE_DENSITY_LB_ADDON = 0.20
+export CORE_UTILIZATION = 50
+export PLACE_DENSITY_LB_ADDON = 0.15
 export TNS_END_PERCENT = 100
 
 export REMOVE_ABC_BUFFERS = 1