Merge branch 'master' into secure-check-finish-setup-tns

Signed-off-by: Jaehyun Kim <[email protected]>

Author: jhkim-pii

docs/user/FlowVariables.md

@@ -367,6 +367,7 @@ configuration file.
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## cts variables
 

flow/designs/rapidus2hp/cva6/config.mk

@@ -64,8 +64,8 @@ export VERILOG_FILES          = $(sort $(wildcard $(SRC_HOME)/common/local/util/
 	$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
 	$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
 	$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
-	$(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim.sv \
-	$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
+	$(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim_half.sv \
+	$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x128m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
 	$(PLATFORM_DIR)/ram/verilog/fakeram7_128x64_shim.sv \
 	$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
 	$(PLATFORM_DIR)/ram/verilog/fakeram7_64x28_shim.sv \
@@ -79,12 +79,12 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include
 
 export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
 
-export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x128m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
 			 $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
 			 $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
 			 $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef
 
-export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
+export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x128m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
 			 $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
 			 $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
 			 $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib
@@ -95,20 +95,7 @@ export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constr
 export SYNTH_HDL_FRONTEND  = slang
 export SYNTH_HIERARCHICAL = 1
 
-ifeq ($(SYNTH_HDL_FRONTEND),verific)
-  # Reduce utilization for verific since it runs into issues with DPL not being
-  # able to place instances or with one-site gap/overlap issues
-  export CORE_UTILIZATION       = 45
-else
-  # Reduce the amount of resizing done between GPL and DPL
-  export EARLY_SIZING_CAP_RATIO = 6
-  ifeq ($(PLACE_SITE),SC6T)
-    # Decrease the utilization so that the tall macros fit
-    export CORE_UTILIZATION       = 50
-  else
-    export CORE_UTILIZATION       = 55
-  endif
-endif
+export CORE_UTILIZATION       = 65
 
 export CORE_MARGIN            = 2
 export MACRO_PLACE_HALO       = 2 2

flow/designs/rapidus2hp/cva6/constraint.sdc

@@ -3,7 +3,7 @@
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
-set clk_period 1200
+set clk_period 1125
 set input_delay 0.46
 set output_delay 0.11
 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

flow/designs/rapidus2hp/ethmac/config.mk

@@ -6,7 +6,7 @@ export VERILOG_FILES         = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NIC
 export SDC_FILE              = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 45
+export CORE_UTILIZATION       = 70
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 0.75
 export PLACE_DENSITY          = 0.70

flow/designs/rapidus2hp/gcd/config.mk

@@ -5,6 +5,6 @@ export PLATFORM    = rapidus2hp
 export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 
-export CORE_UTILIZATION = 30
-export CORE_MARGIN = .75
+export CORE_UTILIZATION = 45
+export CORE_MARGIN = .5
 export PLACE_DENSITY = 0.42

flow/designs/rapidus2hp/gcd/rules-base.json

@@ -12,7 +12,7 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 738,
+        "value": 696,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "finish__timing__setup__ws": {
-        "value": -45.18,
+        "value": -43.47,
         "compare": ">="
     },
     "finish__timing__setup__tns": {

flow/designs/rapidus2hp/ibex/config.mk

@@ -19,7 +19,7 @@ else
 export SDC_FILE              = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 endif
 
-export CORE_UTILIZATION        = 45
+export CORE_UTILIZATION        = 70
 export CORE_ASPECT_RATIO       = 1
 export CORE_MARGIN             = 0.75
 export PLACE_DENSITY_LB_ADDON  = 0.20

flow/designs/rapidus2hp/ibex/rules-base.json

@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "finish__timing__setup__ws": {
-        "value": -134.19,
+        "value": -119.54,
         "compare": ">="
     },
     "finish__timing__setup__tns": {

flow/designs/rapidus2hp/jpeg/config.mk

@@ -8,7 +8,7 @@ export VERILOG_INCLUDE_DIRS   = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 45
+export CORE_UTILIZATION       = 60
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 0.75
 export PLACE_DENSITY          = 0.62

flow/designs/rapidus2hp/jpeg/rules-base.json

@@ -84,7 +84,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -28.2,
+        "value": -26.81,
         "compare": ">="
     }
 }