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add flow/scripts
Signed-off-by: Jack Luar <[email protected]>
1 parent b9d4358 commit 5810f53

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11 files changed

+68
-37
lines changed

11 files changed

+68
-37
lines changed

‎flow/scripts/floorplan.tcl‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,12 @@ append_env_var additional_args ADDITIONAL_SITES -additional_sites 1
4545

4646
set use_floorplan_def [env_var_exists_and_non_empty FLOORPLAN_DEF]
4747
set use_footprint [env_var_exists_and_non_empty FOOTPRINT]
48-
set use_die_and_core_area [expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }]
48+
set use_die_and_core_area \
49+
[expr { [env_var_exists_and_non_empty DIE_AREA] && [env_var_exists_and_non_empty CORE_AREA] }]
4950
set use_core_utilization [env_var_exists_and_non_empty CORE_UTILIZATION]
5051

51-
set methods_defined [expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }]
52+
set methods_defined \
53+
[expr { $use_floorplan_def + $use_footprint + $use_die_and_core_area + $use_core_utilization }]
5254
if { $methods_defined > 1 } {
5355
puts "Error: Floorplan initialization methods are mutually exclusive, pick one."
5456
exit 1

‎flow/scripts/generate_abstract.tcl‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
11
source $::env(SCRIPTS_DIR)/load.tcl
22
erase_non_stage_variables generate_abstract
33

4-
set stem [expr { [env_var_exists_and_non_empty ABSTRACT_SOURCE] ? $::env(ABSTRACT_SOURCE) : "6_final" }]
4+
set stem [expr {
5+
[env_var_exists_and_non_empty ABSTRACT_SOURCE] ?
6+
$::env(ABSTRACT_SOURCE) :
7+
"6_final"
8+
}]
59

610
set result [find_sdc_file $stem.odb]
711
set design_stage [lindex $result 0]

‎flow/scripts/global_route.tcl‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ proc global_route_helper { } {
2525

2626
if { $result != 0 } {
2727
if {
28-
[expr !$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \
28+
[!$::env(GENERATE_ARTIFACTS_ON_FAILURE) || \
2929
![file exists $::global_route_congestion_report] || \
3030
[file size $::global_route_congestion_report] == 0]
3131
} {
@@ -64,7 +64,8 @@ proc global_route_helper { } {
6464
log_cmd global_route -start_incremental
6565
log_cmd detailed_placement
6666
# Route only the modified net by DPL
67-
log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt
67+
log_cmd global_route -end_incremental \
68+
-congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_design.rpt
6869

6970
# Repair timing using global route parasitics
7071
puts "Repair setup and hold violations..."
@@ -81,14 +82,16 @@ proc global_route_helper { } {
8182
log_cmd global_route -start_incremental
8283
log_cmd detailed_placement
8384
# Route only the modified net by DPL
84-
log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt
85+
log_cmd global_route -end_incremental \
86+
-congestion_report_file $::env(REPORTS_DIR)/congestion_post_repair_timing.rpt
8587
}
8688

8789

8890
log_cmd global_route -start_incremental
8991
recover_power_helper
9092
# Route the modified nets by rsz journal restore
91-
log_cmd global_route -end_incremental -congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt
93+
log_cmd global_route -end_incremental \
94+
-congestion_report_file $::env(REPORTS_DIR)/congestion_post_recover_power.rpt
9295

9396
if { ![env_var_equals SKIP_ANTENNA_REPAIR 1] } {
9497
puts "Repair antennas..."

‎flow/scripts/load.tcl‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ proc load_design { design_file sdc_file } {
3333
# Read SDC file
3434
read_sdc $::env(RESULTS_DIR)/$sdc_file
3535

36-
if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
36+
if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } {
3737
log_cmd source $::env(PLATFORM_DIR)/derate.tcl
3838
}
3939

@@ -46,7 +46,7 @@ proc load_design { design_file sdc_file } {
4646
}
4747

4848
#===========================================================================================
49-
# Routines to run equivalence tests when they are enabled.
49+
# Routines to run equivalence tests when they are enabled.
5050

5151
proc get_verilog_cells_for_design { } {
5252
set dir "$::env(PLATFORM_DIR)/work_around_yosys/"
@@ -74,7 +74,8 @@ proc write_eqy_script_for_sky130hd { } {
7474
#[script]
7575
#prep -top aes_cipher_top -flatten
7676

77-
## Using `rename -hide` is a better performing choice than nomatch if the signal names have no meaning at all
77+
## Using `rename -hide` is a better performing choice than nomatch
78+
## if the signal names have no meaning at all
7879
#rename -hide */_*_.*
7980

8081
## This removes unused signals before partitioning so no partitions are created for them
@@ -98,7 +99,7 @@ proc write_eqy_script { } {
9899
# Gold netlist
99100
puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n"
100101
puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
101-
# Modified netlist
102+
# Modified netlist
102103
puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n"
103104
puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
104105

@@ -129,12 +130,14 @@ proc run_equivalence_test { } {
129130
write_eqy_verilog 4_after_rsz.v
130131
write_eqy_script
131132

133+
# tclint-disable-next-line command-args
132134
eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \
133135
--force \
134136
--jobs $::env(NUM_CORES) \
135137
$::env(OBJECTS_DIR)/4_eqy_test.eqy \
136138
> $::env(LOG_DIR)/4_equivalence_check.log
137-
set count [exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log]
139+
set count \
140+
[exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log]
138141
if { $count == 0 } {
139142
error "Repair timing output failed equivalence test"
140143
} else {

‎flow/scripts/open.tcl‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ proc read_timing { input_file } {
2828
set sdc_file $::env(SDC_FILE)
2929
}
3030
log_cmd read_sdc $sdc_file
31-
if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
31+
if { [file exists $::env(PLATFORM_DIR)/derate.tcl] } {
3232
source $::env(PLATFORM_DIR)/derate.tcl
3333
}
3434

@@ -57,7 +57,8 @@ proc read_timing { input_file } {
5757

5858
if { [ord::openroad_gui_compiled] } {
5959
set db_basename [file rootname [file tail $input_file]]
60-
gui::set_title "OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}"
60+
gui::set_title \
61+
"OpenROAD - $::env(PLATFORM)/$::env(DESIGN_NICKNAME)/$::env(FLOW_VARIANT) - ${db_basename}"
6162
}
6263

6364
if { [env_var_equals GUI_TIMING 1] } {

‎flow/scripts/report_metrics.tcl‎

Lines changed: 18 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -45,17 +45,20 @@ proc report_metrics { stage when { include_erc true } { include_clock_skew true
4545
report_puts "\n=========================================================================="
4646
report_puts "$when report_checks -path_delay min"
4747
report_puts "--------------------------------------------------------------------------"
48-
report_checks -path_delay min -fields {slew cap input net fanout} -format full_clock_expanded >> $filename
48+
report_checks -path_delay min -fields {slew cap input net fanout} \
49+
-format full_clock_expanded >> $filename
4950

5051
report_puts "\n=========================================================================="
5152
report_puts "$when report_checks -path_delay max"
5253
report_puts "--------------------------------------------------------------------------"
53-
report_checks -path_delay max -fields {slew cap input net fanout} -format full_clock_expanded >> $filename
54+
report_checks -path_delay max -fields {slew cap input net fanout} \
55+
-format full_clock_expanded >> $filename
5456

5557
report_puts "\n=========================================================================="
5658
report_puts "$when report_checks -unconstrained"
5759
report_puts "--------------------------------------------------------------------------"
58-
report_checks -unconstrained -fields {slew cap input net fanout} -format full_clock_expanded >> $filename
60+
report_checks -unconstrained -fields {slew cap input net fanout} \
61+
-format full_clock_expanded >> $filename
5962

6063
if { $include_erc } {
6164
report_puts "\n=========================================================================="
@@ -154,23 +157,29 @@ proc report_metrics { stage when { include_erc true } { include_clock_skew true
154157
report_puts "\n=========================================================================="
155158
report_puts "$when report_checks -path_delay max reg to reg"
156159
report_puts "--------------------------------------------------------------------------"
157-
report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
160+
report_checks -path_delay max -from [all_registers] -to [all_registers] \
161+
-format full_clock_expanded >> $filename
158162
report_puts "\n=========================================================================="
159163
report_puts "$when report_checks -path_delay min reg to reg"
160164
report_puts "--------------------------------------------------------------------------"
161-
report_checks -path_delay min -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
165+
report_checks -path_delay min -from [all_registers] -to [all_registers] \
166+
-format full_clock_expanded >> $filename
162167

163-
set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
168+
set inp_to_reg_critical_path \
169+
[lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
164170
if { $inp_to_reg_critical_path != "" } {
165-
set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
171+
set target_clock_latency_max \
172+
[sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
166173
} else {
167174
set target_clock_latency_max 0
168175
}
169176

170177

171-
set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0]
178+
set inp_to_reg_critical_path [lindex \
179+
[find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0]
172180
if { $inp_to_reg_critical_path != "" } {
173-
set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
181+
set target_clock_latency_min \
182+
[sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
174183
set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4]
175184
} else {
176185
set target_clock_latency_min 0

‎flow/scripts/resize.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ set pin_count_before [sta::network_leaf_pin_count]
1111
set_dont_use $::env(DONT_USE_CELLS)
1212

1313
if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } {
14-
log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO)
14+
log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO)
1515
}
1616

1717
repair_design_helper

‎flow/scripts/synth.tcl‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,8 @@ set synth_full_args [env_var_or_empty SYNTH_ARGS]
2525
if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } {
2626
set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
2727
} else {
28-
set synth_full_args [concat $synth_full_args "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
28+
set synth_full_args [concat $synth_full_args \
29+
"-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
2930
}
3031

3132
if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
@@ -52,7 +53,8 @@ if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
5253

5354
json -o $::env(RESULTS_DIR)/mem.json
5455
# Run report and check here so as to fail early if this synthesis run is doomed
55-
exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
56+
exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \
57+
--max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
5658

5759
if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
5860
synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args

‎flow/scripts/synth_preamble.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ proc convert_liberty_areas { } {
141141
continue
142142
}
143143
set area [rtlil::get_attr -string -mod $cell area]
144-
if { $found_cell == "" || [expr $area < $found_cell_area] } {
144+
if { $found_cell == "" || [$area < $found_cell_area] } {
145145
set found_cell $cell
146146
set found_cell_area $area
147147
}

‎flow/scripts/util.tcl‎

Lines changed: 17 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
proc log_cmd { cmd args } {
22
# log the command, escape arguments with spaces
3-
set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]"
3+
set log_cmd "$cmd[join [lmap arg $args { format " %s" [expr { [string match {* *} $arg] ? "\"$arg\"" : "$arg" }] }] ""]" ;# tclint-disable-line line-length
44
puts $log_cmd
55
set start [clock seconds]
66
set result [uplevel 1 [list $cmd {*}$args]]
@@ -13,7 +13,7 @@ proc log_cmd { cmd args } {
1313
return $result
1414
}
1515

16-
proc repair_tie_fanout_helper {} {
16+
proc repair_tie_fanout_helper { } {
1717
if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
1818
set tie_separation $env(TIE_SEPARATION)
1919
} else {
@@ -39,7 +39,9 @@ proc fast_route { } {
3939
if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
4040
log_cmd source $::env(FASTROUTE_TCL)
4141
} else {
42-
log_cmd set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT)
42+
log_cmd \
43+
set_global_routing_layer_adjustment \
44+
$::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT)
4345
log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
4446
}
4547
}
@@ -115,7 +117,8 @@ proc find_sdc_file { input_file } {
115117
set sdc_file ""
116118

117119
set exact_sdc [string map {.odb .sdc} $input_file]
118-
set sdc_files [glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"]
120+
set sdc_files \
121+
[glob -nocomplain -directory $::env(RESULTS_DIR) -types f "\[1-9+\]_\[1-9_A-Za-z\]*\.sdc"]
119122
set sdc_files [lsort -decreasing -dictionary $sdc_files]
120123
set sdc_files [lmap file $sdc_files { file normalize $file }]
121124
foreach name $sdc_files {
@@ -175,9 +178,9 @@ proc find_macros { } {
175178
proc erase_non_stage_variables { stage_name } {
176179
# "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of
177180
# variables to erase.
178-
#
181+
#
179182
# Tcl yaml package can't be imported in the sta/openroad environment:
180-
#
183+
#
181184
# https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875
182185
set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name]
183186
foreach var $variables {
@@ -195,11 +198,16 @@ proc place_density_with_lb_addon { } {
195198
set place_density_lb [gpl::get_global_placement_uniform_density \
196199
-pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
197200
-pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)]
198-
set place_density [expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01]
201+
set place_density \
202+
[expr $place_density_lb + ((1.0 - $place_density_lb) * $::env(PLACE_DENSITY_LB_ADDON)) + 0.01]
199203
if { $place_density > 1.0 } {
200-
utl::error FLW 24 "Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = $::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of PLACE_DENSITY_LB_ADDON is between 0 and 0.99."
204+
utl::error FLW 24 \
205+
"Place density exceeds 1.0 (current PLACE_DENSITY_LB_ADDON = \
206+
$::env(PLACE_DENSITY_LB_ADDON)). Please check if the value of \
207+
PLACE_DENSITY_LB_ADDON is between 0 and 0.99."
201208
}
202-
puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON $::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb"
209+
puts "Placement density is $place_density, computed from PLACE_DENSITY_LB_ADDON \
210+
$::env(PLACE_DENSITY_LB_ADDON) and lower bound $place_density_lb"
203211
} else {
204212
set place_density $::env(PLACE_DENSITY)
205213
}

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