docs: Update Ibex source paths

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

docs/tutorials/FlowTutorial.md

@@ -189,13 +189,13 @@ create_clock -name core_clock -period 17.4 [get_ports {clk_i}]
 
 ### Design Input SystemVerilog
 
-The SystemVerilog input files are located in `./designs/src/ibex/`
+The SystemVerilog input files are located in `./designs/src/ibex_sv/`
 
 The design is defined in `ibex_core.sv` available
-[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/ibex_core.v).
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/ibex_core.sv).
 
 Refer to the `ibex` design `README.md`
-[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/README.md).
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/README.md).
 
 ## Running The Automated RTL-to-GDS Flow