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lines changed Original file line number Diff line number Diff line change 11export DESIGN_NAME = ca53_cpu
22export PLATFORM = gf12
33
4+ export SYNTH_HIERARCHICAL = 1
5+ export RTLMP_FLOW = True
6+
47export VERILOG_FILES = $(PLATFORM_DIR ) /$(DESIGN_NAME ) /rtl/ca53_cpu.v
58
69export SDC_FILE = $(PLATFORM_DIR ) /$(DESIGN_NAME ) /sdc/ca53_cpu.sdc
@@ -43,11 +46,15 @@ export ADDITIONAL_GDS += $(PLATFORM_DIR)/$(DESIGN_NAME)/gds2/RFSPHD_A53_HS_128X
4346export DIE_AREA = 0 0 1400 1400
4447export CORE_AREA = 10 10 1390 1390
4548export PLACE_DENSITY_LB_ADDON = 0.05
49+
50+ export HAS_IO_CONSTRAINTS = 1
4651export PLACE_PINS_ARGS = -exclude left :0-600 -exclude left:1350-1400 -exclude right:* -exclude top:* -exclude bottom:*
4752
53+ export MACRO_PLACE_HALO = 7 7
54+ export MACRO_PLACE_CHANNEL = 14 14
55+
4856export MACRO_WRAPPERS = $(dir $(DESIGN_CONFIG ) ) /wrappers.tcl
4957
50- export MACRO_BLOCKAGE_HALO = 25
5158# export MAX_ROUTING_LAYER = H2
5259export FASTROUTE_TCL = $(dir $(DESIGN_CONFIG ) ) /fastroute.tcl
5360#
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