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Merge branch 'master' into secure-update_sta
Signed-off-by: Eder Monteiro <[email protected]>
2 parents da7d964 + 0ff3a4b commit 5dbfa15

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flow/Makefile

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -178,9 +178,6 @@ include $(PLATFORM_DIR)/config.mk
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# is no way to escape space in defaults.py and get "foreach" to work.
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$(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
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# Enables hierarchical yosys
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export SYNTH_STATS = $(RESULTS_DIR)/synth_stats.txt
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export SYNTH_STATS_SCRIPT = $(SCRIPTS_DIR)/synth_stats.tcl
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# If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here
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export MAX_UNGROUP_SIZE ?= 0
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@@ -454,13 +451,6 @@ memory:
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export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
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export SYNTH_MEMORY_MAX_BITS ?= 4096
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.PHONY: do-yosys-stats
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do-yosys-stats:
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mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
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(export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \
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$(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_STATS_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_stats.log)
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export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
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$(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
@@ -487,7 +477,7 @@ $(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES)
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$(UNSET_AND_MAKE) do-yosys-canonicalize
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$(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil
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$(UNSET_AND_MAKE) do-yosys-stats do-yosys
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$(UNSET_AND_MAKE) do-yosys
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.PHONY: do-synth
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do-synth:
@@ -1054,7 +1044,7 @@ klayout:
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.phony: run
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run:
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@mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
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($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) 2>&1 | tee $(abspath $(LOG_DIR)/run.log))
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($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) 2>&1 | tee $(abspath $(LOG_DIR)/$(RUN_LOG_NAME_STEM).log))
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# Utilities
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#-------------------------------------------------------------------------------

flow/designs/asap7/aes-block/metadata-base-ok.json

Lines changed: 243 additions & 245 deletions
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flow/designs/asap7/aes-block/rules-base.json

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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{
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"synth__design__instance__area__stdcell": {
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"value": 2310.54,
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"value": 2293.17,
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"compare": "<="
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},
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"constraints__clocks__count": {
@@ -12,27 +12,27 @@
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 12203,
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"value": 11853,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 1061,
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"value": 1031,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 1061,
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"value": 1031,
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"compare": "<="
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},
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"globalroute__antenna_diodes_count": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__route__wirelength": {
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"value": 98764,
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"value": 88188,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -164.76,
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"value": -198.03,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 7462,
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"value": 7443,
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"compare": "<="
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},
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"finish__timing__drv__setup_violation_count": {
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"value": 531,
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"value": 515,
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {

flow/designs/asap7/mock-array/Element/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ export SDC_FILE = designs/asap7/mock-array/constraints.sdc
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export PLATFORM = asap7
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11-
export PLACE_DENSITY = 0.50
11+
export PLACE_DENSITY = 0.82
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export CORE_AREA = $(shell \
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export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \

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