Tighten rapidus2hp hercules_idecode

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

flow/designs/rapidus2hp/hercules_idecode/config.mk

@@ -14,10 +14,18 @@ export VERILOG_INCLUDE_DIRS =  $(SRC_HOME)/hercules_idecode/verilog \
 export SDC_FILE             = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc
 
 export SYNTH_HDL_FRONTEND  ?= slang
-export CORE_UTILIZATION     = 25
+ifeq ($(SYNTH_HDL_FRONTEND), slang)
+  export CORE_UTILIZATION     = 50
+else
+  export CORE_UTILIZATION     = 48
+endif
+
 export CORE_MARGIN          = 1
 export PLACE_DENSITY        = 0.50
 
 # a smoketest for this option, there are a
 # few last gasp iterations
 export SKIP_LAST_GASP      ?= 1
+
+export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 0
+export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 0

flow/designs/rapidus2hp/hercules_idecode/rules-base.json

@@ -8,7 +8,7 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 13530,
+        "value": 12586,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -30,25 +30,5 @@
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
-    },
-    "finish__timing__setup__ws": {
-        "value": -504.31,
-        "compare": ">="
-    },
-    "finish__design__instance__area": {
-        "value": 13812,
-        "compare": "<="
-    },
-    "finish__timing__drv__setup_violation_count": {
-        "value": 13684,
-        "compare": "<="
-    },
-    "finish__timing__drv__hold_violation_count": {
-        "value": 106,
-        "compare": "<="
-    },
-    "finish__timing__wns_percent_delay": {
-        "value": -75.04,
-        "compare": ">="
     }
 }