Merge remote-tracking branch 'origin/master' into update-metrics

* origin/master:
  sram-64x16: update_ok
  openroad: upgrade to latest master
  sram-64x16: use worst corner and remove unused SRAM
  makefile: add $(SDC_FILE) to 1_1_yosys.v dependencies list
  sram-64x16: test design for MPL2 and clock tree
  mock-array: add automatic formatting
  util: cleanup make issue variables
  util: issue do not save missing path/outside git
  util: make issue do not save CMD, EXE, SHELL
  util: metadata depends on finish
  fix OR submodule
  ci: update failing metrics
  ci: update private PDK metrics
  update OR for this PR
  secure CI/CD for improvements in hold fixing

Author: vvbandeira

flow/Makefile

@@ -406,7 +406,7 @@ ifeq ($(SYNTH_HIERARCHICAL), 1)
 $(RESULTS_DIR)/1_1_yosys.v: $(SYNTH_STOP_MODULE_SCRIPT)
 endif
 
-$(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.sdc &: $(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE)
+$(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.sdc &: $(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE)
 	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
 	($(TIME_CMD) $(YOSYS_CMD) $(YOSYS_FLAGS) -c $(SYNTH_SCRIPT)) 2>&1 | tee $(LOG_DIR)/1_1_yosys.log
 	cp $(SDC_FILE) $(RESULTS_DIR)/1_synth.sdc

flow/designs/asap7/sram-64x16/config.mk

@@ -0,0 +1,37 @@
+export DESIGN_NAME            = SramBridge
+export DESIGN_NICKNAME        = SramBridge
+
+export VERILOG_FILES_BLACKBOX = designs/src/sram-64x16/SRAM2RW16x32.v
+export VERILOG_FILES = designs/src/sram-64x16/*.sv
+
+export SDC_FILE               = designs/asap7/sram-64x16/constraints.sdc
+
+export PLATFORM               = asap7
+
+export PLACE_DENSITY          = 0.30
+
+# match SRAM
+export CORNER = WC
+
+# Pins location, obstruction settings
+  export ADDITIONAL_LEFS = designs/asap7/sram-64x16/lef/SRAM2RW16x32_x4.lef
+# voltage, and temperature (PVT) corner for setup and hold timing analysis
+# contain descriptions of what each pin does, the delays depending on the load given in tables, and power information
+# choose one 'corner'
+export ADDITIONAL_LIBS = designs/asap7/sram-64x16/lib/SRAM2RW16x32_lib/SRAM2RW16x32_PVT_0P63V_100C.lib
+# Entire detailed layout
+export ADDITIONAL_GDS  = designs/asap7/sram-64x16/gds/SRAM2RW16x32_x4.gds
+
+export CORE_UTILIZATION       = 15
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY          = 0.65
+
+export SYNTH_HIERARCHICAL = 1
+export RTLMP_FLOW = True
+
+export DETAILED_ROUTE_ARGS=-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 5
+
+export MACRO_HALO_X            = 3
+export MACRO_HALO_Y            = 3
+#export MACRO_PLACE_HALO        = 3

flow/designs/asap7/sram-64x16/constraints.sdc

@@ -0,0 +1,14 @@
+set sdc_version 2.0
+
+set clk_period 500
+set clk_port_name io_clk
+set clk_name io_clk
+set clk_port [get_ports $clk_port_name]
+create_clock $clk_port -period $clk_period -waveform [list 0 [expr $clk_period/2]]
+
+set clk_io_pct 0.2
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]