asap7/aes-block: demonstrate BLOCKS with shared block.mk

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/asap7/aes-block/autotuner.json

@@ -0,0 +1,100 @@
+{
+    "_SDC_FILE_PATH": "constraint.sdc",
+    "_SDC_CLK_PERIOD": {
+        "type": "float",
+        "minmax": [
+            100,
+            600
+        ],
+        "step": 0
+    },
+    "CORE_UTILIZATION": {
+        "type": "int",
+        "minmax": [
+            30,
+            100
+        ],
+        "step": 1
+    },
+    "CORE_ASPECT_RATIO": {
+        "type": "float",
+        "minmax": [
+            0.5,
+            2.0
+        ],
+        "step": 0
+    },
+    "CORE_MARGIN": {
+        "type": "int",
+        "minmax": [
+            2,
+            2
+        ],
+        "step": 0
+    },
+    "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            5
+        ],
+        "step": 1
+    },
+    "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            5
+        ],
+        "step": 1
+    },
+    "_FR_LAYER_ADJUST": {
+        "type": "float",
+        "minmax": [
+            0.1,
+            0.7
+        ],
+        "step": 0
+    },
+    "PLACE_DENSITY_LB_ADDON": {
+        "type": "float",
+        "minmax": [
+            0.0,
+            0.99
+        ],
+        "step": 0
+    },
+    "_PINS_DISTANCE": {
+        "type": "int",
+        "minmax": [
+            1,
+            4
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_SIZE": {
+        "type": "int",
+        "minmax": [
+            10,
+            200
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_DIAMETER": {
+        "type": "int",
+        "minmax": [
+            20,
+            400
+        ],
+        "step": 1
+    },
+    "_FR_FILE_PATH": "",
+    "_FR_GR_OVERFLOW": {
+        "type": "int",
+        "minmax": [
+            1,
+            1
+        ],
+        "step": 0
+    }
+}

flow/designs/asap7/aes-block/block.mk

@@ -0,0 +1,14 @@
+export PLATFORM               = asap7
+
+export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
+export SDC_FILE      = ./designs/$(PLATFORM)/aes/constraint.sdc
+
+export ABC_AREA               = 1
+
+export CORE_UTILIZATION       = 40 
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY          = 0.70
+
+export PLACE_PINS_ARGS = -annealing
+

flow/designs/asap7/aes-block/config.mk

@@ -0,0 +1,28 @@
+export PLATFORM               = asap7
+
+export DESIGN_NAME            = aes_cipher_top
+export DESIGN_NICKNAME        = aes-block
+
+export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
+export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export ABC_AREA               = 1
+
+export CORE_UTILIZATION       = 10
+export CORE_ASPECT_RATIO      = 1
+export CORE_MARGIN            = 2
+export PLACE_DENSITY          = 0.65
+
+export BLOCKS = aes_rcon aes_sbox
+export SYNTH_HIERARCHICAL = 1
+export RTLMP_FLOW = True
+
+export PLACE_PINS_ARGS = -annealing
+
+# Generous routing at top level
+export MIN_ROUTING_LAYER      = M2
+export MAX_ROUTING_LAYER      = M9
+
+# Ignore power at this exploratory level
+export GND_NETS_VOLTAGES      = ""
+export PWR_NETS_VOLTAGES      = ""

flow/designs/asap7/aes-block/constraint.sdc

@@ -0,0 +1,13 @@
+set clk_name  clk
+set clk_port_name clk
+set clk_period 400 
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]