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lines changed Original file line number Diff line number Diff line change @@ -4,11 +4,6 @@ export PLATFORM = asap7
44
55export SYNTH_HIERARCHICAL ?= 1
66
7- export RTLMP_MIN_INST = 1000
8- export RTLMP_MAX_INST = 3500
9- export RTLMP_MIN_MACRO = 1
10- export RTLMP_MAX_MACRO = 5
11-
127export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
138
149export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME ) /src/riscv32i/* .v) )
Original file line number Diff line number Diff line change @@ -100,10 +100,6 @@ orfs_flow(
100100 arguments = {
101101 "LIB_MODEL" : "CCS" ,
102102 "SYNTH_HIERARCHICAL" : "1" ,
103- "RTLMP_MAX_INST" : "30000" ,
104- "RTLMP_MIN_INST" : "5000" ,
105- "RTLMP_MAX_MACRO" : "30" ,
106- "RTLMP_MIN_MACRO" : "4" ,
107103 "DIE_AREA" : "0 0 550 600" ,
108104 "CORE_AREA" : "5 5 545 595" ,
109105 "PLACE_PINS_ARGS" : "-exclude left:* -exclude right:*" ,
Original file line number Diff line number Diff line change @@ -42,12 +42,6 @@ export SYNTH_KEEP_MODULES ?= \
4242 ram_256x34
4343
4444
45- # RTL_MP Settings
46- export RTLMP_MAX_INST = 30000
47- export RTLMP_MIN_INST = 5000
48- export RTLMP_MAX_MACRO = 30
49- export RTLMP_MIN_MACRO = 4
50-
5145export LIB_MODEL = CCS
5246
5347export VERILOG_FILES = $(DESIGN_HOME ) /src/swerv/swerv_wrapper.sv2v.v \
Original file line number Diff line number Diff line change @@ -4,12 +4,6 @@ export PLATFORM = nangate45
44
55export SYNTH_HIERARCHICAL = 1
66
7- # RTL_MP Settings
8- export RTLMP_MAX_INST = 30000
9- export RTLMP_MIN_INST = 5000
10- export RTLMP_MAX_MACRO = 16
11- export RTLMP_MIN_MACRO = 4
12-
137export VERILOG_FILES = $(DESIGN_HOME ) /src/$(DESIGN_NICKNAME ) /ariane.sv2v.v \
148 $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NICKNAME ) /macros.v
159
Original file line number Diff line number Diff line change @@ -5,10 +5,6 @@ export PLATFORM = nangate45
55export SYNTH_HIERARCHICAL = 1
66
77# RTL_MP Settings
8- export RTLMP_MAX_INST = 30000
9- export RTLMP_MIN_INST = 5000
10- export RTLMP_MAX_MACRO = 16
11- export RTLMP_MIN_MACRO = 4
128export RTLMP_SIGNATURE_NET_THRESHOLD = 30
139
1410export VERILOG_FILES = $(DESIGN_HOME ) /src/$(DESIGN_NICKNAME ) /ariane.sv2v.v \
Original file line number Diff line number Diff line change @@ -4,11 +4,6 @@ export PLATFORM = nangate45
44
55export SYNTH_HIERARCHICAL = 1
66#
7- # RTL_MP Settings
8- export RTLMP_MAX_INST = 30000
9- export RTLMP_MIN_INST = 5000
10- export RTLMP_MAX_MACRO = 12
11- export RTLMP_MIN_MACRO = 4
127
138export VERILOG_FILES = $(DESIGN_HOME ) /src/$(DESIGN_NAME ) /pickled.v \
149 $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NAME ) /macros.v
Original file line number Diff line number Diff line change @@ -4,11 +4,6 @@ export PLATFORM = nangate45
44
55export SYNTH_HIERARCHICAL = 1
66#
7- # RTL_MP Settings
8- export RTLMP_MAX_INST = 30000
9- export RTLMP_MIN_INST = 5000
10- export RTLMP_MAX_MACRO = 12
11- export RTLMP_MIN_MACRO = 4
127
138export VERILOG_FILES = $(DESIGN_HOME ) /src/$(DESIGN_NAME ) /pickled.v \
149 $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NAME ) /macros.v
Original file line number Diff line number Diff line change @@ -4,11 +4,6 @@ export PLATFORM = nangate45
44
55export SYNTH_HIERARCHICAL = 1
66#
7- # RTL_MP Settings
8- export RTLMP_MAX_INST = 30000
9- export RTLMP_MIN_INST = 5000
10- export RTLMP_MAX_MACRO = 12
11- export RTLMP_MIN_MACRO = 4
127
138export VERILOG_FILES = $(DESIGN_HOME ) /src/$(DESIGN_NAME ) /pickled.v \
149 $(DESIGN_HOME ) /$(PLATFORM ) /$(DESIGN_NAME ) /macros.v
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