Skip to content

Commit 70eafd3

Browse files
authored
Merge pull request #2907 from Pinata-Consulting/smaller-artifacts
flow: avoid DONT_USE_SC_LIB as an artifact between steps
2 parents bae8656 + 87eecbf commit 70eafd3

File tree

2 files changed

+10
-6
lines changed

2 files changed

+10
-6
lines changed

flow/Makefile

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -337,7 +337,7 @@ $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
337337
@mkdir -p $(OBJECTS_DIR)/lib
338338
$(UTILS_DIR)/preprocessLib.py -i $^ -o $@
339339

340-
$(OBJECTS_DIR)/lib/merged.lib:
340+
$(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS)
341341
$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
342342

343343
# Pre-process KLayout tech
@@ -437,19 +437,19 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
437437
mkdir -p $(dir $@)
438438
echo $(ABC_CLOCK_PERIOD_IN_PS) > $@
439439

440-
YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
440+
YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
441441

442442
.PHONY: yosys-dependencies
443443
yosys-dependencies: $(YOSYS_DEPENDENCIES)
444444

445445
.PHONY: do-yosys
446-
do-yosys:
446+
do-yosys: $(DONT_USE_SC_LIB)
447447
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
448448
(export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \
449449
$(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys.log)
450450

451451
.PHONY: do-yosys-canonicalize
452-
do-yosys-canonicalize: yosys-dependencies
452+
do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB)
453453
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
454454
($(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SCRIPTS_DIR)/synth_canonicalize.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_canonicalize.log)
455455

@@ -594,7 +594,7 @@ endef
594594

595595
# STEP 1: Translate verilog to odb
596596
#-------------------------------------------------------------------------------
597-
$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan))
597+
$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(DONT_USE_SC_LIB),floorplan))
598598

599599
# STEP 2: Random IO placement
600600
#-------------------------------------------------------------------------------
@@ -619,7 +619,7 @@ $(eval $(call do-copy,2_floorplan,2_5_floorplan_pdn.odb,))
619619
$(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.odb
620620

621621
.PHONY: do-floorplan
622-
do-floorplan:
622+
do-floorplan: $(DONT_USE_SC_LIB)
623623
$(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_io do-2_3_floorplan_macro do-2_4_floorplan_tapcell do-2_5_floorplan_pdn do-2_floorplan do-2_floorplan.sdc
624624

625625
.PHONY: clean_floorplan

flow/platforms/asap7/config.mk

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,10 @@ export LIB_FILES += $(ADDITIONAL_LIBS)
263263
export DB_FILES += $(realpath $($(CORNER)_DB_FILES))
264264
export TEMPERATURE = $($(CORNER)_TEMPERATURE)
265265
export VOLTAGE = $($(CORNER)_VOLTAGE)
266+
267+
# FIXME Need merged.lib for now, but ideally it shouldn't be necessary:
268+
#
269+
# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/2139
266270
export DONT_USE_SC_LIB = $(OBJECTS_DIR)/lib/merged.lib
267271

268272
# ---------------------------------------------------------

0 commit comments

Comments
 (0)