Merge remote-tracking branch 'origin/master' into arian136_add

Author: vijayank88

docker/Dockerfile.runtime

@@ -2,7 +2,8 @@
 # binaries.
 FROM openroad/centos7-runtime
 RUN yum update -y \
+    && yum install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm \
     && yum group install -y "Development Tools" \
     && yum install -y https://www.klayout.org/downloads/CentOS_7/klayout-0.27.1-0.x86_64.rpm \
-    && yum install -y time tcl-devel \
+    && yum install -y tcl tcl-tclreadline-devel tcllib time \
     && pip3 install pandas

flow/designs/asap7/ethmac/constraint.sdc

@@ -1,13 +1,29 @@
-set clk_name wb_clk_i 
-set clk_port_name wb_clk_i 
-set clk_period 960
+set top_clk_name wb_clk_i
+set clk_period 1500
 set clk_io_pct 0.2
+set clk_port [get_ports $top_clk_name]
+create_clock -name $top_clk_name -period $clk_period $clk_port
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
 
-set clk_port [get_ports $clk_port_name]
-
-create_clock -name $clk_name -period $clk_period $clk_port
+set tx_clk_name mtx_clk_pad_i
+set tx_clk_port [get_ports $tx_clk_name]
+set tx_clk_period 500
+create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
+set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
+set_input_delay  [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs 
+set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set rx_clk_name mrx_clk_pad_i
+set rx_clk_port [get_ports $rx_clk_name]
+set rx_clk_period 500
+create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
+set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
+set_input_delay  [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs 
+set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
 
-set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+set_clock_groups -name core_clock -logically_exclusive \
+ -group [get_clocks $top_clk_name] \
+ -group [get_clocks $tx_clk_name] \
+ -group [get_clocks $rx_clk_name]

flow/designs/asap7/ethmac/metadata-base-ok.json

@@ -4,11 +4,11 @@
         "compare": "<="
     },
     "constraints__clocks__count": {
-        "value": 1,
+        "value": 3,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 8748,
+        "value": 8744,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -20,15 +20,15 @@
         "compare": "=="
     },
     "cts__timing__setup__ws": {
-        "value": 0.0,
+        "value": -127.74,
         "compare": ">="
     },
     "cts__timing__setup__ws__pre_repair": {
-        "value": -260.92,
+        "value": -214.98,
         "compare": ">="
     },
     "cts__timing__setup__ws__post_repair": {
-        "value": -260.92,
+        "value": -214.98,
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
@@ -39,32 +39,28 @@
         "value": 2888,
         "compare": "<="
     },
-    "globalroute__timing__clock__slack": {
-        "value": -151.29,
-        "compare": ">="
-    },
     "globalroute__timing__setup__ws": {
-        "value": -151.29,
+        "value": -47.32,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 254225,
+        "value": 250905,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
         "value": 0,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -246.63,
+        "value": 0.0,
         "compare": ">="
     },
     "finish__design__instance__area": {
         "value": 8803,
         "compare": "<="
     },
     "finish__timing__drv__max_slew_limit": {
-        "value": -1.32,
+        "value": -0.57,
         "compare": ">="
     },
     "finish__timing__drv__max_fanout_limit": {
@@ -84,7 +80,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -23.22,
+        "value": -10.0,
         "compare": ">="
     }
-}
+}

flow/designs/asap7/ethmac/rules-base.json

@@ -1,64 +1,64 @@
-ces_0_0 R0 10 10
-ces_0_1 R0 35 10
-ces_0_2 R0 60 10
-ces_0_3 R0 85 10
-ces_0_4 R0 110 10
-ces_0_5 R0 135 10
-ces_0_6 R0 160 10
-ces_0_7 R0 185 10
-ces_1_0 R0 10 35
-ces_1_1 R0 35 35
-ces_1_2 R0 60 35
-ces_1_3 R0 85 35
-ces_1_4 R0 110 35
-ces_1_5 R0 135 35
-ces_1_6 R0 160 35
-ces_1_7 R0 185 35
-ces_2_0 R0 10 60
-ces_2_1 R0 35 60
-ces_2_2 R0 60 60
-ces_2_3 R0 85 60
-ces_2_4 R0 110 60
-ces_2_5 R0 135 60
-ces_2_6 R0 160 60
-ces_2_7 R0 185 60
-ces_3_0 R0 10 85
-ces_3_1 R0 35 85
-ces_3_2 R0 60 85
-ces_3_3 R0 85 85
-ces_3_4 R0 110 85
-ces_3_5 R0 135 85
-ces_3_6 R0 160 85
-ces_3_7 R0 185 85
-ces_4_0 R0 10 110
-ces_4_1 R0 35 110
-ces_4_2 R0 60 110
-ces_4_3 R0 85 110
-ces_4_4 R0 110 110
-ces_4_5 R0 135 110
-ces_4_6 R0 160 110
-ces_4_7 R0 185 110
-ces_5_0 R0 10 135
-ces_5_1 R0 35 135
-ces_5_2 R0 60 135
-ces_5_3 R0 85 135
-ces_5_4 R0 110 135
-ces_5_5 R0 135 135
-ces_5_6 R0 160 135
-ces_5_7 R0 185 135
-ces_6_0 R0 10 160
-ces_6_1 R0 35 160
-ces_6_2 R0 60 160
-ces_6_3 R0 85 160
-ces_6_4 R0 110 160
-ces_6_5 R0 135 160
-ces_6_6 R0 160 160
-ces_6_7 R0 185 160
-ces_7_0 R0 10 185
-ces_7_1 R0 35 185
-ces_7_2 R0 60 185
-ces_7_3 R0 85 185
-ces_7_4 R0 110 185
-ces_7_5 R0 135 185
-ces_7_6 R0 160 185
-ces_7_7 R0 185 185
+ces_0_0 R0 9.792 9.792
+ces_0_1 R0 34.560 9.792
+ces_0_2 R0 59.328 9.792
+ces_0_3 R0 84.096 9.792
+ces_0_4 R0 108.864 9.792
+ces_0_5 R0 133.632 9.792
+ces_0_6 R0 158.400 9.792
+ces_0_7 R0 183.168 9.792
+ces_1_0 R0 9.792 34.560
+ces_1_1 R0 34.560 34.560
+ces_1_2 R0 59.328 34.560
+ces_1_3 R0 84.096 34.560
+ces_1_4 R0 108.864 34.560
+ces_1_5 R0 133.632 34.560
+ces_1_6 R0 158.400 34.560
+ces_1_7 R0 183.168 34.560
+ces_2_0 R0 9.792 59.328
+ces_2_1 R0 34.560 59.328
+ces_2_2 R0 59.328 59.328
+ces_2_3 R0 84.096 59.328
+ces_2_4 R0 108.864 59.328
+ces_2_5 R0 133.632 59.328
+ces_2_6 R0 158.400 59.328
+ces_2_7 R0 183.168 59.328
+ces_3_0 R0 9.792 84.096
+ces_3_1 R0 34.560 84.096
+ces_3_2 R0 59.328 84.096
+ces_3_3 R0 84.096 84.096
+ces_3_4 R0 108.864 84.096
+ces_3_5 R0 133.632 84.096
+ces_3_6 R0 158.400 84.096
+ces_3_7 R0 183.168 84.096
+ces_4_0 R0 9.792 108.864
+ces_4_1 R0 34.560 108.864
+ces_4_2 R0 59.328 108.864
+ces_4_3 R0 84.096 108.864
+ces_4_4 R0 108.864 108.864
+ces_4_5 R0 133.632 108.864
+ces_4_6 R0 158.400 108.864
+ces_4_7 R0 183.168 108.864
+ces_5_0 R0 9.792 133.632
+ces_5_1 R0 34.560 133.632
+ces_5_2 R0 59.328 133.632
+ces_5_3 R0 84.096 133.632
+ces_5_4 R0 108.864 133.632
+ces_5_5 R0 133.632 133.632
+ces_5_6 R0 158.400 133.632
+ces_5_7 R0 183.168 133.632
+ces_6_0 R0 9.792 158.400
+ces_6_1 R0 34.560 158.400
+ces_6_2 R0 59.328 158.400
+ces_6_3 R0 84.096 158.400
+ces_6_4 R0 108.864 158.400
+ces_6_5 R0 133.632 158.400
+ces_6_6 R0 158.400 158.400
+ces_6_7 R0 183.168 158.400
+ces_7_0 R0 9.792 183.168
+ces_7_1 R0 34.560 183.168
+ces_7_2 R0 59.328 183.168
+ces_7_3 R0 84.096 183.168
+ces_7_4 R0 108.864 183.168
+ces_7_5 R0 133.632 183.168
+ces_7_6 R0 158.400 183.168
+ces_7_7 R0 183.168 183.168