mock-array: read_power_activities MockArray.vcd test case

To do post synthesis simulation and use read_power_activities for
report_power, run:

make DESIGN_CONFIG=designs/asap7/mock-array/config.mk final simulate power

This is a starting point for collaboration of separate concerns
that will be addressed in multiple PRs that try to address a single
concern at the time:

- Where should the behavioral .v files for ASAP7 go?
- The simulation needs to happen for every build. Today this happens using Chisel,
  but it would be better to use Verilator to provide an example that can
  be reused for other designs. Although users may generate Verilog using
  tools such as XLS, Aramanth, Chisel, etc., ORFS takes Verilog as read and
  is not involved in this process.
- Add post synthesis report_power after read_power_activities for asap7/gcd
- What to do about read_spef for Element, currently commented out?
- Regression testing should include read_power_activities report_power for the
  designs that support it.
- The power.tcl is currently hard-coded to mock-array, make it general so that
  it works for all designs, including those that use BLOCKS
- The "power" and "simulate" targets are specific to mock-array, make them
  generic and have some default behavior when for designs it is not used.
- The behavioral model of ASAP7 is not supported by Verilator. ChatGPT seems
  to be able to whip up a behavioral model easily, but where should these
  files go? I don't think it makes sense to try to update ASAP7, I think these
  files are specific to ORFS.

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/asap7/mock-array/config.mk

@@ -40,6 +40,16 @@ verilog:
 	export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
 	./designs/asap7/mock-array/verilog.sh
 
+.PHONY: simulate
+simulate:
+	export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \
+	export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
+	./designs/asap7/mock-array/simulate.sh
+
+.PHONY: power
+power:
+	$(OPENSTA_EXE) -no_init -exit designs/asap7/mock-array/power.tcl
+
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 12 iterations were needed for 0
 # violations.

flow/designs/asap7/mock-array/power.tcl

@@ -0,0 +1,18 @@
+foreach libFile $::env(LIB_FILES) {
+read_liberty $libFile
+}
+
+read_verilog results/asap7/mock-array_Element/base/6_final.v
+read_verilog $::env(RESULTS_DIR)/6_final.v
+read_verilog designs/src/mock-array/post/empty.v
+
+link_design MockArray
+
+read_sdc $::env(RESULTS_DIR)/6_final.sdc
+read_spef $::env(RESULTS_DIR)/6_final.spef
+# FIXME lots of warnings
+#read_spef results/asap7/mock-array_Element/base/6_final.spef
+
+report_power
+read_power_activities -scope TOP/MockArrayTestbench/postSynthesis -vcd designs/src/mock-array/MockArrayTestbench.vcd
+report_power

flow/designs/asap7/mock-array/simulate.sh

@@ -0,0 +1,19 @@
+#!/usr/bin/env bash
+set -ex
+
+# allow this script to be invoked from any folder
+DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
+BASE=$DIR/../..
+
+cd $DIR
+
+cd ../../src/mock-array
+cp ../../../results/asap7/mock-array/base/6_final.v post/MockArrayFinal.v
+cp ../../../results/asap7/mock-array_Element/base/6_final.v post/MockArrayElementFinal.v
+
+pwd
+sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
+     "test:runMain SimulatePostSynthesis --width ${MOCK_ARRAY_COLS} --height ${MOCK_ARRAY_ROWS} --dataWidth ${MOCK_ARRAY_DATAWIDTH}"
+
+cp test_run_dir/MockArray_should_Wiggle_some_wires/MockArrayTestbench.vcd .
+

flow/designs/asap7/mock-array/verilog.sh

@@ -14,3 +14,8 @@ sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
 
 # reduce git noise as these comments will change if the line numbers in Chisel changes
 find . -name "*.v" -type f -exec sed -i 's/ \/\/.*$//' {} \;
+
+sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
+     "test:runMain GenerateMockArray --width ${MOCK_ARRAY_COLS} --height ${MOCK_ARRAY_ROWS} --dataWidth ${MOCK_ARRAY_DATAWIDTH} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
+
+cp test_run_dir/MockArray_should_Wiggle_some_wires/MockArray.vcd .

flow/designs/src/mock-array/post/.gitignore

@@ -0,0 +1 @@
+MockArray*.v