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bazel: cleanup
works: bazel build ... Signed-off-by: Øyvind Harboe <[email protected]>
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‎flow/BUILD.bazel‎

Lines changed: 41 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
load("@rules_python//python:pip.bzl", "compile_pip_requirements")
21
load("@bazel-orfs//:openroad.bzl", "orfs_flow")
2+
load("@rules_python//python:pip.bzl", "compile_pip_requirements")
33

44
filegroup(
55
name = "constraints-gcd",
@@ -26,10 +26,9 @@ orfs_flow(
2626
stage_sources = {
2727
"synth": [":constraints-gcd"],
2828
},
29-
verilog_files = glob(include=["designs/src/gcd/*.v"]),
29+
verilog_files = glob(include = ["designs/src/gcd/*.v"]),
3030
)
3131

32-
3332
filegroup(
3433
name = "constraints-swerv",
3534
srcs = [
@@ -38,30 +37,26 @@ filegroup(
3837
visibility = [":__subpackages__"],
3938
)
4039

41-
filegroup(
42-
name = "swerv-fastroute",
43-
srcs = [
44-
"designs/asap7/swerv_wrapper/fastroute.tcl",
45-
],
46-
visibility = [":__subpackages__"],
47-
)
48-
4940
filegroup(
5041
name = "additional_lefs",
51-
srcs = glob(include=["designs/asap7/swerv_wrapper/lef/*.lef"])
42+
srcs = glob(include = ["designs/asap7/swerv_wrapper/lef/*.lef"]),
5243
)
44+
5345
filegroup(
5446
name = "additional_libs",
55-
srcs = glob(include=["designs/asap7/swerv_wrapper/lib/*.lib"])
47+
srcs = glob(include = ["designs/asap7/swerv_wrapper/lib/*.lib"]),
5648
)
5749

5850
SWERV_ALL = {
59-
"LIB_MODEL":"CCS",
51+
"LIB_MODEL": "CCS",
6052
"ADDITIONAL_LEFS": "$(locations :additional_lefs)",
6153
"ADDITIONAL_LIBS": "$(locations :additional_libs)",
6254
}
6355

64-
all_sources = [":additional_lefs", ":additional_libs"]
56+
all_sources = [
57+
":additional_lefs",
58+
":additional_libs",
59+
]
6560

6661
orfs_flow(
6762
name = "swerv_wrapper",
@@ -77,7 +72,7 @@ orfs_flow(
7772
"RTLMP_MIN_MACRO": "4",
7873
"DIE_AREA": "0 0 550 600",
7974
"CORE_AREA": "5 5 545 595",
80-
"PLACE_PINS_ARGS": "-exclude left:* -exclude right:*"
75+
"PLACE_PINS_ARGS": "-exclude left:* -exclude right:*",
8176
},
8277
"place": SWERV_ALL | {
8378
"PLACE_PINS_ARGS": "-exclude left:* -exclude right:*",
@@ -86,29 +81,26 @@ orfs_flow(
8681
"cts": SWERV_ALL | {
8782
"TNS_END_PERCENT": "100",
8883
},
89-
"route": SWERV_ALL | {
90-
"FASTROUTE_TCL": "$(location :swerv-fastroute)",
91-
},
84+
"route": SWERV_ALL,
9285
"final": SWERV_ALL | {
9386
"PWR_NETS_VOLTAGEsS": "",
9487
"GND_NETS_VOLTAGES": "",
95-
}
88+
},
9689
},
97-
verilog_files = glob(include=[
98-
"designs/src/swerv/swerv_wrapper.sv2v.v",
99-
"designs/asap7/swerv_wrapper/macros.v"
100-
]),
10190
stage_sources = {
10291
"synth": all_sources + [":constraints-swerv"],
10392
"floorplan": all_sources,
10493
"place": all_sources,
10594
"cts": all_sources,
106-
"route": all_sources + [":swerv-fastroute"],
95+
"route": all_sources,
10796
"final": all_sources,
10897
},
98+
verilog_files = glob(include = [
99+
"designs/src/swerv/swerv_wrapper.sv2v.v",
100+
"designs/asap7/swerv_wrapper/macros.v",
101+
]),
109102
)
110103

111-
112104
filegroup(
113105
name = "mock-array-constraints",
114106
srcs = [
@@ -120,34 +112,26 @@ filegroup(
120112
filegroup(
121113
name = "mock-array-io",
122114
srcs = [
123-
"designs/asap7/mock-array/io.tcl"
115+
"designs/asap7/mock-array/io.tcl",
124116
],
125117
data = [
126118
"designs/src/mock-array/util.tcl",
127119
],
128120
visibility = [":__subpackages__"],
129121
)
130122

131-
filegroup(
132-
name = "mock-array-fastroute",
133-
srcs = [
134-
"designs/asap7/mock-array/fastroute.tcl",
135-
],
136-
visibility = [":__subpackages__"],
137-
)
138-
139123
MOCK_ARRAY_FLOORPLAN_PLACE = {
140124
"PLACE_PINS_ARGS": "-annealing",
141125
"IO_CONSTRAINTS": "$(location :mock-array-io)",
142126
"PLACE_DENSITY": "0.30",
143-
"DIE_AREA": "0 0 358.56 388.8",
144-
"CORE_AREA": "2.16 2.16 356.40000000000003 386.64000000000004",
145-
"MACRO_PLACE_HALO": "0 2.16",
146-
"RTLMP_BOUNDARY_WT": "0",
147-
"PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl",
148-
"MACRO_HALO_X": "0.5",
149-
"MACRO_HALO_Y": "0.5",
150-
"MACRO_BLOCKAGE_HALO": "0",
127+
"DIE_AREA": "0 0 358.56 388.8",
128+
"CORE_AREA": "2.16 2.16 356.40000000000003 386.64000000000004",
129+
"MACRO_PLACE_HALO": "0 2.16",
130+
"RTLMP_BOUNDARY_WT": "0",
131+
"PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl",
132+
"MACRO_HALO_X": "0.5",
133+
"MACRO_HALO_Y": "0.5",
134+
"MACRO_BLOCKAGE_HALO": "0",
151135
"ADDITIONAL_FILES": "$(locations :mock-array-io)",
152136
}
153137

@@ -163,12 +147,11 @@ orfs_flow(
163147
"place": MOCK_ARRAY_FLOORPLAN_PLACE | {
164148
},
165149
"cts": {
166-
"CTS_BUF_DISTANCE": "60"
150+
"CTS_BUF_DISTANCE": "60",
167151
},
168152
"route": {
169-
"FASTROUTE_TCL": "$(location :mock-array-fastroute)",
170153
# works with 28 or more iterations as of writing, so give it a few more.
171-
"GLOBAL_ROUTE_ARGS" : "-congestion_iterations 40 -verbose",
154+
"GLOBAL_ROUTE_ARGS": "-congestion_iterations 40 -verbose",
172155
# If this design isn't quickly done in detailed routing, something is wrong.
173156
# At time of adding this option, only 12 iterations were needed for 0
174157
# violations.
@@ -182,24 +165,22 @@ orfs_flow(
182165
"GDS_ALLOW_EMPTY": "Element",
183166
"PWR_NETS_VOLTAGEsS": "",
184167
"GND_NETS_VOLTAGES": "",
185-
}
168+
},
186169
},
187-
verilog_files = glob(include=["designs/src/mock-array/*.v"]),
188170
stage_sources = {
189171
"synth": all_sources + [":mock-array-constraints"] + [":mock-array-io"],
190172
"floorplan": all_sources + [":mock-array-io"],
191173
"place": all_sources + [":mock-array-io"],
192174
"cts": all_sources,
193-
"route": all_sources + [":mock-array-fastroute"],
194175
"final": all_sources,
195176
},
177+
verilog_files = glob(include = ["designs/src/mock-array/*.v"]),
196178
)
197179

198-
199180
filegroup(
200181
name = "mock-array-element-io",
201182
srcs = [
202-
"designs/asap7/mock-array/Element/io.tcl"
183+
"designs/asap7/mock-array/Element/io.tcl",
203184
],
204185
data = [
205186
"designs/src/mock-array/util.tcl",
@@ -209,20 +190,22 @@ filegroup(
209190

210191
MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE = {
211192
"IO_CONSTRAINTS": "$(location :mock-array-element-io)",
212-
"PLACE_DENSITY": "0.50",
213193
"PLACE_PINS_ARGS": "-annealing",
214194
}
215195

216196
MOCK_ARRAY_ELEMENT_ALL = {
217-
"MOCK_ARRAY_ROWS" : "8",
218-
"MOCK_ARRAY_COLS" : "8",
197+
"MOCK_ARRAY_ROWS": "8",
198+
"MOCK_ARRAY_COLS": "8",
219199
}
220200

221201
mock_array_all_sources = ["designs/src/mock-array/util.tcl"]
222202

223203
orfs_flow(
224204
name = "Element",
225205
abstract_stage = "route",
206+
arguments = {
207+
"PLACE_DENSITY": "0.82",
208+
},
226209
stage_arguments = {
227210
"synth": MOCK_ARRAY_ELEMENT_ALL | {
228211
"SDC_FILE": "$(location :mock-array-constraints)",
@@ -249,23 +232,22 @@ orfs_flow(
249232
"final": MOCK_ARRAY_ELEMENT_ALL | {
250233
"PWR_NETS_VOLTAGES": "",
251234
"GND_NETS_VOLTAGES": "",
252-
}
235+
},
253236
},
254-
verilog_files = glob(include=["designs/src/mock-array/*.v"]),
255237
stage_sources = {
256238
"synth": mock_array_all_sources + [":mock-array-constraints"],
257239
"floorplan": mock_array_all_sources + [":mock-array-element-io"],
258240
"place": mock_array_all_sources + [":mock-array-element-io"],
259241
"cts": mock_array_all_sources,
260-
"route": mock_array_all_sources + [":mock-array-fastroute"],
242+
"route": mock_array_all_sources,
261243
"final": mock_array_all_sources,
262244
},
245+
verilog_files = glob(include = ["designs/src/mock-array/*.v"]),
263246
)
264247

265-
266248
filegroup(
267249
name = "ethmac_lvt_src",
268-
srcs = glob(include=["designs/src/ethmac_lvt/*.v"]),
250+
srcs = glob(include = ["designs/src/ethmac_lvt/*.v"]),
269251
visibility = [":__subpackages__"],
270252
)
271253

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