Merge pull request #2417 from Pinata-Consulting/config-purge

maliberty · web-flow · commit 789bc39fb53e · 2024-10-03T16:25:36.000-07:00
config: purge unused HAS_IO_CONSTRAINTS
diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk
@@ -11,4 +11,3 @@ export CORE_MARGIN            = 2
 export PLACE_DENSITY          = 0.70
 
 export PLACE_PINS_ARGS = -annealing
-export HAS_IO_CONSTRAINTS = 0
diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk
@@ -18,7 +18,6 @@ export SYNTH_HIERARCHICAL = 1
 export RTLMP_FLOW = 1
 
 export PLACE_PINS_ARGS = -annealing
-export HAS_IO_CONSTRAINTS = 0
 
 # Generous routing at top level
 export MIN_ROUTING_LAYER      = M2
diff --git a/flow/designs/src/mock-alu/defaults.mk b/flow/designs/src/mock-alu/defaults.mk
@@ -16,4 +16,3 @@ verilog:
 	./designs/src/mock-alu/verilog.sh
 
 export PLACE_PINS_ARGS=-annealing
-export HAS_IO_CONSTRAINTS=0
diff --git a/flow/designs/tsmc65lp/bp_fe_top/config.mk b/flow/designs/tsmc65lp/bp_fe_top/config.mk
@@ -25,7 +25,6 @@ export ADDITIONAL_GDS  = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg6_w8_bit.gds2 \
 export DIE_AREA    = 0 0 880 780 
 export CORE_AREA   = 10 12 870 770
 export PLACE_PINS_ARGS = -exclude left:* -exclude right:0-400 -exclude bottom:*
-export HAS_IO_CONSTRAINTS = 0
 
 export MACRO_PLACE_HALO = 10 10
 export MACRO_PLACE_CHANNEL = 20 20

Original file line number	Diff line number	Diff line change
`@@ -11,4 +11,3 @@ export CORE_MARGIN = 2`
`11`	`11`	`export PLACE_DENSITY = 0.70`
`12`	`12`
`13`	`13`	`export PLACE_PINS_ARGS = -annealing`
`14`		`-export HAS_IO_CONSTRAINTS = 0`
Original file line number	Diff line number	Diff line change
`@@ -16,4 +16,3 @@ verilog:`
`16`	`16`	`./designs/src/mock-alu/verilog.sh`
`17`	`17`
`18`	`18`	`export PLACE_PINS_ARGS=-annealing`
`19`		`-export HAS_IO_CONSTRAINTS=0`