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oharboeoharboe
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Merge remote-tracking branch 'origin/master' into HEAD
2 parents e7377ba + d682200 commit 7a6ee73

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5 files changed

+110
-58
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5 files changed

+110
-58
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‎flow/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -406,7 +406,7 @@ ifeq ($(SYNTH_HIERARCHICAL), 1)
406406
$(RESULTS_DIR)/1_1_yosys.v: $(SYNTH_STOP_MODULE_SCRIPT)
407407
endif
408408

409-
$(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.sdc &: $(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE)
409+
$(RESULTS_DIR)/1_1_yosys.v $(RESULTS_DIR)/1_synth.sdc &: $(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE)
410410
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
411411
($(TIME_CMD) $(YOSYS_CMD) $(YOSYS_FLAGS) -c $(SYNTH_SCRIPT)) 2>&1 | tee $(LOG_DIR)/1_1_yosys.log
412412
cp $(SDC_FILE) $(RESULTS_DIR)/1_synth.sdc

‎flow/designs/src/mock-array/.scalafmt.conf‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
version = "3.7.10"
2+
runner.dialect = scala213

‎flow/designs/src/mock-array/src/test/scala/MockArray.scala‎

Lines changed: 53 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ object Routes extends Enumeration {
2020
val LEFT, UP, RIGHT, DOWN = Value
2121
}
2222

23-
class RoutesVec(singleElementWidth:Int) extends Record {
23+
class RoutesVec(singleElementWidth: Int) extends Record {
2424
val routes = SeqMap(Routes.values.toSeq.map { bus =>
2525
bus -> UInt(singleElementWidth.W)
2626
}: _*)
@@ -30,20 +30,22 @@ class RoutesVec(singleElementWidth:Int) extends Record {
3030
def asSeq: Seq[UInt] = routes.map(_._2).toSeq
3131
}
3232

33-
class BusesVec(singleElementWidth:Int, width:Int, height:Int) extends Record {
34-
val routes = SeqMap(Routes.LEFT -> Vec(height, UInt(singleElementWidth.W)),
33+
class BusesVec(singleElementWidth: Int, width: Int, height: Int)
34+
extends Record {
35+
val routes = SeqMap(
36+
Routes.LEFT -> Vec(height, UInt(singleElementWidth.W)),
3537
Routes.RIGHT -> Vec(height, UInt(singleElementWidth.W)),
3638
Routes.UP -> Vec(width, UInt(singleElementWidth.W)),
37-
Routes.DOWN -> Vec(width, UInt(singleElementWidth.W)),
39+
Routes.DOWN -> Vec(width, UInt(singleElementWidth.W))
3840
)
3941
val elements = routes.map { case (a, b) => a.toString().toLowerCase() -> b }
4042

4143
def asMap: SeqMap[Routes.Value, Vec[UInt]] = routes
4244
def asSeq: Seq[Vec[UInt]] = routes.map(_._2).toSeq
4345
}
4446

45-
46-
class MockArray(width:Int, height:Int, singleElementWidth:Int) extends Module {
47+
class MockArray(width: Int, height: Int, singleElementWidth: Int)
48+
extends Module {
4749
val io = IO(new Bundle {
4850
val ins = Input(new BusesVec(singleElementWidth, width, height))
4951
val outs = Output(new BusesVec(singleElementWidth, width, height))
@@ -64,35 +66,50 @@ class MockArray(width:Int, height:Int, singleElementWidth:Int) extends Module {
6466
// Registered routing paths
6567
// left <-> down
6668
// up <-> right
67-
(io.outs.asSeq zip io.ins.asSeq.reverse.map(RegNext(_))).foreach{case (a, b) => a := b}
69+
(io.outs.asSeq zip io.ins.asSeq.reverse.map(RegNext(_))).foreach {
70+
case (a, b) => a := b
71+
}
6872

6973
// Combinational logic
7074
io.lsbOuts := io.lsbIns.drop(1) ++ Seq(io.outs.asSeq.head(0)(0))
7175
}
7276

7377
val ces = Seq.fill(height)(Seq.fill(width)(Module(new Element())))
7478

75-
ces.foreach{row =>
79+
ces.foreach { row =>
7680
row.head.io.lsbIns := DontCare
7781
if (row.length > 1) {
78-
row.sliding(2, 1).foreach{pair =>
82+
row.sliding(2, 1).foreach { pair =>
7983
pair(1).io.lsbIns := pair(0).io.lsbOuts
84+
}
8085
}
81-
}}
86+
}
8287

8388
io.lsbs := RegNext(VecInit(ces.map(_.last.io.lsbOuts).flatten))
8489

8590
// Connect inputs to edge element buses
86-
(ces.map(_.head).map(_.io.ins.asMap(Routes.RIGHT)) zip io.ins.asMap(Routes.RIGHT)).foreach { case (a, b) => a := b }
87-
(ces.last.map(_.io.ins.asMap(Routes.DOWN)) zip io.ins.asMap(Routes.DOWN)).foreach { case (a, b) => a := b }
88-
(ces.map(_.last).map(_.io.ins.asMap(Routes.LEFT)) zip io.ins.asMap(Routes.LEFT)).foreach { case (a, b) => a := b }
89-
(ces.head.map(_.io.ins.asMap(Routes.UP)) zip io.ins.asMap(Routes.UP)).foreach { case (a, b) => a := b }
91+
(ces.map(_.head).map(_.io.ins.asMap(Routes.RIGHT)) zip io.ins.asMap(
92+
Routes.RIGHT
93+
)).foreach { case (a, b) => a := b }
94+
(ces.last.map(_.io.ins.asMap(Routes.DOWN)) zip io.ins.asMap(Routes.DOWN))
95+
.foreach { case (a, b) => a := b }
96+
(ces.map(_.last).map(_.io.ins.asMap(Routes.LEFT)) zip io.ins.asMap(
97+
Routes.LEFT
98+
)).foreach { case (a, b) => a := b }
99+
(ces.head.map(_.io.ins.asMap(Routes.UP)) zip io.ins.asMap(Routes.UP))
100+
.foreach { case (a, b) => a := b }
90101

91102
// Connect edge element buses to outputs
92-
(ces.map(_.head).map(_.io.outs.asMap(Routes.LEFT)) zip io.outs.asMap(Routes.LEFT)).foreach { case (a, b) => b := a }
93-
(ces.last.map(_.io.outs.asMap(Routes.UP)) zip io.outs.asMap(Routes.UP)).foreach { case (a, b) => b := a }
94-
(ces.map(_.last).map(_.io.outs.asMap(Routes.RIGHT)) zip io.outs.asMap(Routes.RIGHT)).foreach { case (a, b) => b := a }
95-
(ces.head.map(_.io.outs.asMap(Routes.DOWN)) zip io.outs.asMap(Routes.DOWN)).foreach { case (a, b) => b := a }
103+
(ces.map(_.head).map(_.io.outs.asMap(Routes.LEFT)) zip io.outs.asMap(
104+
Routes.LEFT
105+
)).foreach { case (a, b) => b := a }
106+
(ces.last.map(_.io.outs.asMap(Routes.UP)) zip io.outs.asMap(Routes.UP))
107+
.foreach { case (a, b) => b := a }
108+
(ces.map(_.last).map(_.io.outs.asMap(Routes.RIGHT)) zip io.outs.asMap(
109+
Routes.RIGHT
110+
)).foreach { case (a, b) => b := a }
111+
(ces.head.map(_.io.outs.asMap(Routes.DOWN)) zip io.outs.asMap(Routes.DOWN))
112+
.foreach { case (a, b) => b := a }
96113

97114
// Connect neighboring left/right element buses
98115
(ces.transpose.flatten zip ces.transpose.drop(1).flatten).foreach {
@@ -102,18 +119,21 @@ class MockArray(width:Int, height:Int, singleElementWidth:Int) extends Module {
102119
}
103120

104121
// Connect neighboring up/down element buses
105-
(ces.flatten zip ces.drop(1).flatten).foreach {
106-
case (a, b) =>
107-
a.io.ins.asMap(Routes.DOWN) := b.io.outs.asMap(Routes.DOWN)
108-
b.io.ins.asMap(Routes.UP) := a.io.outs.asMap(Routes.UP)
122+
(ces.flatten zip ces.drop(1).flatten).foreach { case (a, b) =>
123+
a.io.ins.asMap(Routes.DOWN) := b.io.outs.asMap(Routes.DOWN)
124+
b.io.ins.asMap(Routes.UP) := a.io.outs.asMap(Routes.UP)
109125
}
110126
}
111127

112-
case class ArrayConfig(width: Int = 8, height: Int = 8, dataWidth: Int = 8, remainingArgs: Seq[String] = Seq.empty)
128+
case class ArrayConfig(
129+
width: Int = 8,
130+
height: Int = 8,
131+
dataWidth: Int = 8,
132+
remainingArgs: Seq[String] = Seq.empty
133+
)
113134

114135
object GenerateMockArray extends App {
115136

116-
117137
val builder = OParser.builder[ArrayConfig]
118138
val parser = {
119139
import builder._
@@ -142,9 +162,15 @@ object GenerateMockArray extends App {
142162

143163
OParser.parse(parser, configArgs, ArrayConfig()) match {
144164
case Some(c) =>
145-
146-
new ChiselStage()
147-
.execute(chiselArgs, Seq(ChiselGeneratorAnnotation(() => new MockArray(c.width, c.height, c.dataWidth))))
165+
new ChiselStage()
166+
.execute(
167+
chiselArgs,
168+
Seq(
169+
ChiselGeneratorAnnotation(() =>
170+
new MockArray(c.width, c.height, c.dataWidth)
171+
)
172+
)
173+
)
148174

149175
case _ =>
150176
// arguments are invalid

‎flow/util/generate-vars.sh‎

Lines changed: 36 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4,22 +4,47 @@ DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
44

55
# exclude system and CI variables
66
EXCLUDED_VARS="MAKE|PYTHONPATH|PKG_CONFIG_PATH|PERL5LIB|PCP_DIR|PATH|MANPATH"
7-
EXCLUDED_VARS+="|LD_LIBRARY_PATH|INFOPATH|HOME|PWD|MAIL|TIME_CMD|QT_QPA_PLATFORM"
8-
EXCLUDED_VARS+="|do-step|get_variables|do-copy"
7+
EXCLUDED_VARS+="|LD_LIBRARY_PATH|INFOPATH|HOME|PWD|MAIL|QT_QPA_PLATFORM"
8+
EXCLUDED_VARS+="|OPENROAD_CMD|OPENROAD_GUI_CMD|OPENROAD_NO_EXIT_CMD"
9+
EXCLUDED_VARS+="|LSORACLE_CMD|YOSYS_CMD|TIME_CMD|STDBUF_CMD"
10+
EXCLUDED_VARS+="|SHELL|OPENROAD_EXE|YOSYS_EXE"
11+
EXCLUDED_VARS+="|NPROC|NUM_CORES|PUBLIC|CURDIR|ISSUE_SCRIPTS|MAKEFLAGS"
12+
EXCLUDED_VARS+="|UNSET_VARIABLES_NAMES|do-step|get_variables|do-copy"
913

14+
# get the root directory of the Git repository
15+
GIT_ROOT=$(git rev-parse --show-toplevel)
16+
FLOW_ROOT=${GIT_ROOT}/flow
1017
printf '%s\n' "$ISSUE_VARIABLES" | while read -r V;
1118
do
12-
if [[ ! ${V%=*} =~ ^[[:digit:]] && ${V} == *"="* && ! -z ${V#*=} && ${V%=*} != *"MAKEFILE"* && ! ${V%=*} =~ ^(${EXCLUDED_VARS})$ ]] ; then
13-
rhs=`sed -e 's/^"//' -e 's/"$//' <<<"${V#*=}"`
14-
# handle special case where the variable needs to be splitted in Tcl code
15-
if [[ "${V%=*}" == "GND_NETS_VOLTAGES" || "${V%=*}" == "PWR_NETS_VOLTAGES" ]]; then
16-
echo "export "${V%=*}"='"\"${rhs}"\"'" >> $1.sh;
17-
else
18-
echo "export "${V%=*}"='"${rhs}"'" >> $1.sh;
19+
if [[ ${V%=*} =~ ^[[:digit:]] || ${V} != *"="* || -z ${V#*=} || ${V%=*} == *"MAKEFILE"* || ${V%=*} =~ ^(${EXCLUDED_VARS})$ ]] ; then
20+
continue
21+
fi
22+
rhs=`sed -e 's/^"//' -e 's/"$//' <<<"${V#*=}"`
23+
if [[ "${rhs}" == "''" ]]; then
24+
echo "Skiping empty variable ${V}"
25+
continue
26+
fi
27+
# handle absolute paths
28+
if [[ "${rhs}" == /* ]]; then
29+
if [[ ! -e "${rhs}" ]]; then
30+
echo "Skiping path not found ${V}"
31+
continue
1932
fi
20-
echo "set env("${V%=*}") \""${rhs}\""" >> $1.tcl;
21-
echo "set env "${V%=*}" "${rhs}"" >> $1.gdb;
33+
if [[ "${rhs}" != "${GIT_ROOT}"* ]]; then
34+
echo "Skiping file outside git ${V}"
35+
continue
36+
fi
37+
# convert the absolute path to a path relative to the flow dir
38+
rhs=$(realpath --relative-to="$FLOW_ROOT" "$rhs")
39+
fi
40+
# handle special case where the variable needs to be splitted in Tcl code
41+
if [[ "${V%=*}" == "GND_NETS_VOLTAGES" || "${V%=*}" == "PWR_NETS_VOLTAGES" ]]; then
42+
echo "export "${V%=*}"='"\"${rhs}"\"'" >> $1.sh;
43+
else
44+
echo "export "${V%=*}"='"${rhs}"'" >> $1.sh;
2245
fi
46+
echo "set env("${V%=*}") \""${rhs}\""" >> $1.tcl;
47+
echo "set env "${V%=*}" "${rhs}"" >> $1.gdb;
2348
done
2449

2550
# remove variables starting with a dot

‎flow/util/utils.mk‎

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,40 +1,39 @@
11
# Utilities
22
#===============================================================================
33
.PHONY: metadata
4-
metadata: $(REPORTS_DIR)/metadata-$(FLOW_VARIANT)-check.log
4+
metadata: finish
5+
@echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt
6+
@$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \
7+
-p $(PLATFORM) \
8+
-v $(FLOW_VARIANT) \
9+
-o $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json 2>&1 \
10+
| tee $(REPORTS_DIR)/gen-metrics-$(FLOW_VARIANT)-check.log
11+
@$(UTILS_DIR)/checkMetadata.py \
12+
-m $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json \
13+
-r $(dir $(DESIGN_CONFIG))rules-$(FLOW_VARIANT).json 2>&1 \
14+
| tee $(REPORTS_DIR)/metadata-$(FLOW_VARIANT)-check.log
515

616
.PHONY: clean_metadata
717
clean_metadata:
818
rm -f $(REPORTS_DIR)/metadata-$(FLOW_VARIANT)-check.log
919
rm -f $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json
1020

11-
.PHONY: update_metadata update_rules update_ok
21+
.PHONY: update_ok
1222
update_ok: update_metadata update_rules
1323

14-
update_metadata: $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json
24+
.PHONY: update_metadata
25+
update_metadata: metadata
1526
cp -f $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json \
1627
$(DESIGN_DIR)/metadata-$(FLOW_VARIANT)-ok.json
1728

18-
update_rules:
29+
.PHONY: update_rules
30+
update_rules: metadata
1931
$(UTILS_DIR)/genRuleFile.py $(DESIGN_DIR) --variant $(FLOW_VARIANT) --failing --tighten
2032

2133
.PHONY: update_rules_force
22-
update_rules_force:
34+
update_rules_force: metadata
2335
$(UTILS_DIR)/genRuleFile.py $(DESIGN_DIR) --variant $(FLOW_VARIANT) --update
2436

25-
$(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json: $(wildcard $(LOG_DIR)/*.json) \
26-
$(wildcard $(LOG_DIR)/*.log) $(REPORTS_DIR)/synth_stat.txt
27-
echo $(DESIGN_DIR) > $(REPORTS_DIR)/design-dir.txt
28-
$(UTILS_DIR)/genMetrics.py -d $(DESIGN_NICKNAME) \
29-
-p $(PLATFORM) \
30-
-v $(FLOW_VARIANT) \
31-
-o $@ 2>&1 | tee $(REPORTS_DIR)/gen-metrics-$(FLOW_VARIANT)-check.log
32-
33-
RULES_DESIGN = $(dir $(DESIGN_CONFIG))rules-$(FLOW_VARIANT).json
34-
35-
$(REPORTS_DIR)/metadata-$(FLOW_VARIANT)-check.log: $(REPORTS_DIR)/metadata-$(FLOW_VARIANT).json
36-
$(UTILS_DIR)/checkMetadata.py -m $< -r $(RULES_DESIGN) 2>&1 | tee $@
37-
3837
#-------------------------------------------------------------------------------
3938

4039
.PHONY: write_net_rc
@@ -101,7 +100,7 @@ $(foreach script,$(ISSUE_SCRIPTS),$(script)_issue): %_issue : versions.txt
101100
clean_issues:
102101
rm -rf $(foreach issue, $(ISSUE_SCRIPTS), $(issue)_*.tar.gz)
103102
rm -rf $(VARS_BASENAME).sh $(RUN_ME_SCRIPT)
104-
103+
105104
$(RESULTS_DIR)/6_final_only_clk.def: $(RESULTS_DIR)/6_final.def
106105
$(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/deleteNonClkNets.tcl
107106

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