Merge remote-tracking branch 'origin/master' into asap7-dont-use

Author: povik

dev_env.sh

@@ -3,7 +3,7 @@
 # Set developer paths and environment variables here,
 # user settings go in ./env.sh
 function __setpaths() {
-    local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")")
+    local DIR=$(readlink -f "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")")
     [ "$(find $DIR/dependencies -type f -user root)" ] && echo "WARNING! Files set up by sudo found in $DIR"
     export PATH="$DIR/dependencies/bin:$PATH"
     export CMAKE_INSTALL_RPATH=$DIR/dependencies/lib:$DIR/dependencies/lib64

docs/user/FlowVariables.md

@@ -174,6 +174,7 @@ configuration file.
 | <a name="PLATFORM"></a>PLATFORM| Specifies process design kit or technology node to be used.| |
 | <a name="PLATFORM_TCL"></a>PLATFORM_TCL| Specifies a Tcl script with commands to run before loading design.| |
 | <a name="POST_CTS_TCL"></a>POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| |
+| <a name="PRE_GLOBAL_ROUTE_TCL"></a>PRE_GLOBAL_ROUTE_TCL| Specifies a Tcl script with commands to run before global route.| |
 | <a name="PROCESS"></a>PROCESS| Technology node or process in use.| |
 | <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| |
 | <a name="RCX_RULES"></a>RCX_RULES| RC Extraction rules file path.| |
@@ -213,14 +214,17 @@ configuration file.
 | <a name="SETUP_SLACK_MARGIN"></a>SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0|
 | <a name="SET_RC_TCL"></a>SET_RC_TCL| Metal & Via RC definition file path.| |
 | <a name="SKIP_CTS_REPAIR_TIMING"></a>SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| |
+| <a name="SKIP_DETAILED_ROUTE"></a>SKIP_DETAILED_ROUTE| Skips detailed route.| 0|
 | <a name="SKIP_GATE_CLONING"></a>SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| |
 | <a name="SKIP_INCREMENTAL_REPAIR"></a>SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0|
 | <a name="SKIP_LAST_GASP"></a>SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| |
 | <a name="SKIP_PIN_SWAP"></a>SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| |
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
+| <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| |
+| <a name="SYNTH_CANONICALIZE_TCL"></a>SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| |
 | <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0|
@@ -235,7 +239,7 @@ configuration file.
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| |
 | <a name="TIEHI_CELL_AND_PORT"></a>TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| |
 | <a name="TIELO_CELL_AND_PORT"></a>TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| |
-| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| |
+| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| 0|
 | <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
 | <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
 | <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
@@ -255,7 +259,9 @@ configuration file.
 - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
+- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
+- [SYNTH_CANONICALIZE_TCL](#SYNTH_CANONICALIZE_TCL)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
@@ -322,9 +328,11 @@ configuration file.
 - [SKIP_LAST_GASP](#SKIP_LAST_GASP)
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [TAPCELL_TCL](#TAPCELL_TCL)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
+- [TIE_SEPARATION](#TIE_SEPARATION)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## place variables
@@ -346,7 +354,7 @@ configuration file.
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
-- [TIE_SEPARATION](#TIE_SEPARATION)
+- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 
 ## cts variables
 
@@ -382,6 +390,7 @@ configuration file.
 - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
 - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER)
 - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
+- [PRE_GLOBAL_ROUTE_TCL](#PRE_GLOBAL_ROUTE_TCL)
 - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE)
@@ -403,6 +412,7 @@ configuration file.
 - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
 - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
+- [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 
 ## final variables

env.sh

@@ -1,9 +1,9 @@
 #!/usr/bin/env bash
 function __setpaths() {
   if [[ "$OSTYPE" == "darwin"* ]]; then
-    DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]}"))"
+    DIR="$(dirname $(perl -e 'use Cwd "abs_path";print abs_path(shift)' "${BASH_SOURCE[0]:-${(%):-%x}}"))"
   else
-    DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]}"))"
+    DIR="$(dirname $(readlink -f "${BASH_SOURCE[0]:-${(%):-%x}}"))"
   fi
 
   export OPENROAD=${DIR}/tools/OpenROAD

etc/DependencyInstaller.sh

@@ -235,7 +235,7 @@ _help() {
     cat <<EOF
 
 All arguments and flags are only applicable for OpenROAD dependencies
-Usage: $0
+Usage: $0 [-all|-base|-common] [-<ARGS>]
                                 # Installs all of OpenROAD's dependencies no
                                 #     need to run -base or -common. Requires
                                 #     privileged access.

flow/Makefile

@@ -550,7 +550,7 @@ grt: $(RESULTS_DIR)/5_1_grt.odb
 
 # STEP 1: Run global route
 #-------------------------------------------------------------------------------
-$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE),global_route))
+$(eval $(call do-step,5_1_grt,$(RESULTS_DIR)/4_cts.odb $(FASTROUTE_TCL) $(PRE_GLOBAL_ROUTE_TCL),global_route))
 
 # STEP 2: Run detailed route
 #-------------------------------------------------------------------------------

flow/designs/asap7/aes-block/config.mk

@@ -8,10 +8,10 @@ export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
 
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 20
+export CORE_UTILIZATION       = 40
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 2
-export PLACE_DENSITY          = 0.60
+export PLACE_DENSITY          = 0.53
 
 export BLOCKS ?= aes_rcon aes_sbox
 export SYNTH_HIERARCHICAL = 1
@@ -27,6 +27,6 @@ export GND_NETS_VOLTAGES      =
 export PWR_NETS_VOLTAGES      =
 
 # The macros are very small so use a smaller halo
-export MACRO_PLACE_HALO        ?= 5 5
+export MACRO_PLACE_HALO        ?= 3 3
 
 export ROUTING_LAYER_ADJUSTMENT = 0.3

flow/designs/asap7/aes-block/rules-base.json

@@ -1,38 +1,38 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 2131.37,
+        "value": 2130.06,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 7290,
+        "value": 7258,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 11004,
+        "value": 10666,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 957,
+        "value": 928,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1561,
+        "value": 985,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 75984,
+        "value": 62805,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -152.45,
+        "value": -63.56,
         "compare": ">="
     },
     "finish__design__instance__area": {
         "value": 7348,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 478,
+        "value": 464,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -18.47,
+        "value": -17.84,
         "compare": ">="
     }
 }

flow/designs/asap7/cva6/canonicalize.tcl

@@ -0,0 +1,4 @@
+# Remove rvfi_probes_o interface since contributes 4k ports and connections
+# (many of which are buffers tied to tie cells)
+
+delete cva6/o:rvfi_probes_o*

flow/designs/asap7/cva6/config.mk

@@ -105,3 +105,6 @@ export SYNTH_HDL_FRONTEND = slang
 export ASAP7_USE_VT = RVT LVT SLVT
 
 export CTS_LIB_NAME = asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120
+
+# Remove rvfi_probes_o interface
+export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl

flow/designs/asap7/cva6/rules-base.json

@@ -1,38 +1,38 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 19725.15,
+        "value": 18975.35,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 20690,
+        "value": 19709,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 136421,
+        "value": 123443,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 11863,
+        "value": 10734,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 11863,
+        "value": 10734,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1074578,
+        "value": 716033,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,15 +48,15 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -139.89,
+        "value": -82.95,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 20850,
+        "value": 19864,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 5931,
+        "value": 5367,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {