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2 parents c37e10a + bf8d312 commit 7cc98e6Copy full SHA for 7cc98e6
flow/designs/src/mock-alu/src/test/resources/README.md
@@ -2,5 +2,5 @@ ASAP7 behavioral model files
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============================
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To run unit-tests, copy the behavioral model Verilog files from ASAP7
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-from https://github.com/The-OpenROAD-Project/asap7/tree/master/asap7sc7p5t_28/Verilog
+from https://github.com/The-OpenROAD-Project/asap7sc7p5t_28/tree/main/Verilog
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into this folder.
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