synth: use SYNTH_KEEP_MODULES for consistency

and introduce a test-case.

Also, the keep attribute is set at the same time as
SYNTH_HIERARCHICAL=1 for consistency

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

docs/user/FlowVariables.md

@@ -131,7 +131,6 @@ configuration file.
 | <a name="PLACE_SITE"></a>PLACE_SITE| Placement site for core cells defined in the technology LEF file.| | |
 | <a name="PLATFORM"></a>PLATFORM| Specifies process design kit or technology node to be used.| | |
 | <a name="POST_CTS_TCL"></a>POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| | |
-| <a name="PRESERVE_CELLS"></a>PRESERVE_CELLS| Mark modules to keep from getting removed in flattening.| | |
 | <a name="PROCESS"></a>PROCESS| Technology node or process in use.| | |
 | <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | |
 | <a name="RCX_RULES"></a>RCX_RULES| RC Extraction rules file path.| | |
@@ -181,6 +180,7 @@ configuration file.
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
+| <a name="SYNTH_KEEP_MODULES"></a>SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
 | <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| | |
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
@@ -211,6 +211,7 @@ configuration file.
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
+- [SYNTH_KEEP_MODULES](#SYNTH_KEEP_MODULES)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
 - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE)
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
@@ -400,7 +401,6 @@ configuration file.
 - [LIB_FILES](#LIB_FILES)
 - [MACRO_EXTENSION](#MACRO_EXTENSION)
 - [PLATFORM](#PLATFORM)
-- [PRESERVE_CELLS](#PRESERVE_CELLS)
 - [PROCESS](#PROCESS)
 - [RCX_RULES](#RCX_RULES)
 - [RECOVER_POWER](#RECOVER_POWER)

flow/designs/asap7/swerv_wrapper/config.mk

@@ -1,7 +1,41 @@
 export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = asap7
 
-export SYNTH_HIERARCHICAL = 1
+# The list below is a manual keep policy:
+# make SYNTH_HIERARCHICAL=1 SYNTH_KEEP_MODULES= clean_synth synth
+# make run-yosys RUN_YOSYS_ARGS=-C
+
+# % ls A:keep_hierarchy=1
+export SYNTH_KEEP_MODULES ?= \
+  IC_DATA_ICACHE_TAG_HIGH12_ICACHE_TAG_LOW6_ICACHE_IC_DEPTH8 \
+  IC_TAG_ICACHE_TAG_HIGH12_ICACHE_TAG_LOW6_ICACHE_TAG_DEPTH64 \
+  dbg \
+  dec_decode_ctl \
+  dec_gpr_ctl_GPR_BANKS1_GPR_BANKS_LOG21 \
+  dec_ib_ctl \
+  dec_tlu_ctl \
+  dec_trigger \
+  dma_ctrl \
+  exu \
+  exu_alu_ctl \
+  exu_div_ctl \
+  ifu_aln_ctl \
+  ifu_bp_ctl \
+  ifu_ifc_ctl \
+  ifu_mem_ctl \
+  lsu_bus_buffer \
+  lsu_bus_intf \
+  lsu_dccm_ctl \
+  lsu_dccm_mem \
+  lsu_ecc \
+  lsu_lsc_ctl \
+  lsu_stbuf \
+  lsu_trigger \
+  pic_ctrl \
+  ram_2048x39 \
+  ram_256x34
+
+
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
 export RTLMP_MIN_INST = 5000

flow/scripts/synth.tcl

@@ -8,6 +8,14 @@ if { [env_var_equals SYNTH_GUT 1] } {
   delete $::env(DESIGN_NAME)/c:*
 }
 
+if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} {
+  foreach module $::env(SYNTH_KEEP_MODULES) {
+    select -module $module
+    setattr -mod -set keep_hierarchy 1
+    select -clear
+  }
+}
+
 if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
   # Perform standard coarse-level synthesis script, flatten right away
   # (-flatten part of $synth_args per default)

flow/scripts/synth_preamble.tcl

@@ -63,16 +63,6 @@ if {[env_var_exists_and_non_empty SYNTH_BLACKBOXES]} {
   }
 }
 
-# Mark modules to keep from getting removed in flattening
-if {[env_var_exists_and_non_empty PRESERVE_CELLS]} {
-  hierarchy -check -top $::env(DESIGN_NAME)
-  foreach cell $::env(PRESERVE_CELLS) {
-    select -module $cell
-    setattr -mod -set keep_hierarchy 1
-    select -clear
-  }
-}
-
 if {$::env(ABC_AREA)} {
   puts "Using ABC area script."
   set abc_script $::env(SCRIPTS_DIR)/abc_area.script

flow/scripts/variables.yaml

@@ -644,9 +644,11 @@ DFF_LIB_FILES:
 DONT_USE_LIBS:
   description: |
     Set liberty files as `dont_use`.
-PRESERVE_CELLS:
+SYNTH_KEEP_MODULES:
   description: |
     Mark modules to keep from getting removed in flattening.
+  stages:
+    - synth
 SYNTH_ARGS:
   description: |
     Optional synthesis variables for yosys.