Update clk constraints for asap7 (aes, gcd) and sky130hd (ibex, jpeg) to get slightly neg slack at finish; update metadata

Signed-off-by: Ravi Varadarajan <[email protected]>

Author: ravi-varadarajan

flow/designs/asap7/aes/constraint.sdc

@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 500 
+set clk_period 400 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/aes/metadata-base-ok.json

@@ -32,19 +32,19 @@
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 1105,
+        "value": 1449,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
         "value": 1105,
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
-        "value": -35.7,
+        "value": -88.28,
         "compare": ">="
     },
     "globalroute__timing__setup__ws": {
-        "value": -35.7,
+        "value": -88.28,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
@@ -56,7 +56,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -46.35,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/aes/rules-base.json

@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name  core_clock
 set clk_port_name clk
-set clk_period 400 
+set clk_period 390 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/gcd/constraint.sdc

@@ -20,7 +20,7 @@
         "compare": "=="
     },
     "cts__timing__setup__ws": {
-        "value": -150.09,
+        "value": -118.69,
         "compare": ">="
     },
     "cts__timing__setup__ws__pre_repair": {

flow/designs/asap7/gcd/metadata-base-ok.json

@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 17.4 
+set clk_period 15.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/gcd/rules-base.json

@@ -8,7 +8,7 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 181202,
+        "value": 180956,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -40,39 +40,39 @@
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
-        "value": 0.0,
+        "value": -1.71,
         "compare": ">="
     },
     "globalroute__timing__setup__ws": {
-        "value": 0.0,
+        "value": -1.72,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 738923,
+        "value": 738284,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
         "value": 0,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -1.76,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 183447,
+        "value": 183149,
         "compare": "<="
     },
     "finish__timing__drv__max_slew_limit": {
-        "value": -0.49,
+        "value": -0.42,
         "compare": ">="
     },
     "finish__timing__drv__max_fanout_limit": {
         "value": -0.2,
         "compare": ">="
     },
     "finish__timing__drv__max_cap_limit": {
-        "value": -0.34,
+        "value": -0.31,
         "compare": ">="
     },
     "finish__timing__drv__setup_violation_count": {

flow/designs/sky130hd/ibex/constraint.sdc

@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 9.0 
+set clk_period 8.0 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]