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Merge branch 'master' of https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts into secure-drt_layer_range
2 parents f53efc1 + a950e2b commit 7e77235

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docs/user/FlowVariables.md

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@@ -214,6 +214,7 @@ configuration file.
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| <a name="SETUP_SLACK_MARGIN"></a>SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0|
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| <a name="SET_RC_TCL"></a>SET_RC_TCL| Metal & Via RC definition file path.| |
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| <a name="SKIP_CTS_REPAIR_TIMING"></a>SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| |
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| <a name="SKIP_DETAILED_ROUTE"></a>SKIP_DETAILED_ROUTE| Skips detailed route.| 0|
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| <a name="SKIP_GATE_CLONING"></a>SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| |
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| <a name="SKIP_INCREMENTAL_REPAIR"></a>SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0|
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| <a name="SKIP_LAST_GASP"></a>SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| |
@@ -411,6 +412,7 @@ configuration file.
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- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
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- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW)
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- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
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- [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE)
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- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
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## final variables

flow/designs/rapidus2hp/cva6/config.mk

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@@ -102,7 +102,12 @@ ifeq ($(SYNTH_HDL_FRONTEND),verific)
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else
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# Reduce the amount of resizing done between GPL and DPL
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export EARLY_SIZING_CAP_RATIO = 6
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export CORE_UTILIZATION = 55
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ifeq ($(TRACK_OPTION),6T)
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# Decrease the utilization so that the tall macros fit
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export CORE_UTILIZATION = 50
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else
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export CORE_UTILIZATION = 55
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endif
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endif
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export CORE_MARGIN = 2

flow/designs/rapidus2hp/ethmac/constraint.sdc

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@@ -22,7 +22,7 @@ set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
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set rx_clk_name mrx_clk_pad_i
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set rx_clk_port [get_ports $rx_clk_name]
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set rx_clk_period 300
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set rx_clk_period 200
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create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
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set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
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$rx_clk_port]

flow/designs/rapidus2hp/gcd/constraint.sdc

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@@ -2,7 +2,7 @@ current_design gcd
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set clk_name core_clock
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set clk_port_name clk
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set clk_period 185
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set clk_period 150
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]

flow/designs/rapidus2hp/hercules_is_int/config.mk

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@@ -22,7 +22,11 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects
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export SYNTH_HDL_FRONTEND = slang
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export SYNTH_HIERARCHICAL ?= 0
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export CORE_UTILIZATION = 35
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ifeq ($(TRACK_OPTION), 6T)
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export CORE_UTILIZATION = 30
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else
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export CORE_UTILIZATION = 35
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endif
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export CORE_MARGIN = 2
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export MACRO_PLACE_HALO = 2 2

flow/scripts/detail_route.tcl

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@@ -5,6 +5,12 @@ if { ![grt::have_routes] } {
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error "Global routing failed, run `make gui_grt` and load $::global_route_congestion_report \
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in DRC viewer to view congestion"
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}
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if { [env_var_exists_and_non_empty SKIP_DRT] } {
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write_db $::env(RESULTS_DIR)/5_2_route.odb
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exit
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}
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erase_non_stage_variables route
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set_propagated_clock [all_clocks]
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flow/scripts/final_report.tcl

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write_verilog $::env(RESULTS_DIR)/6_final.v
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# Run extraction and STA
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if { [env_var_exists_and_non_empty RCX_RULES] } {
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if {
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[env_var_exists_and_non_empty RCX_RULES]
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&& ![env_var_exists_and_non_empty SKIP_DRT]
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} {
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# RCX section
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define_process_corner -ext_model_index 0 X
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extract_parasitics -ext_model_file $::env(RCX_RULES)

flow/scripts/variables.yaml

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config.mk or from bazel-orfs.
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stages:
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- test
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SKIP_DETAILED_ROUTE:
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default: 0
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description: >
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Skips detailed route.
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stages:
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- route

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