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povikpovik
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Merge branch 'master' into bump-yosys-slang
2 parents ce7b280 + 9699a49 commit 7f81ad0

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‎.github/workflows/github-actions-lint-tcl.yml‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,12 @@ jobs:
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- name: Install Dependencies
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run: |
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python3 -m pip install -U --user tclint==0.4.2
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python3 -m venv venv
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venv/bin/pip install tclint==0.4.2
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- name: Lint
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run: |
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source venv/bin/activate
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tclfmt --version
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tclfmt --in-place .
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git diff --exit-code

‎.github/workflows/github-actions-manual-update-rules.yml‎

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@@ -22,12 +22,14 @@ jobs:
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python-version: "3.10"
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- name: Install Python Packages
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run: |
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pip install firebase-admin
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python3 -m venv venv
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venv/bin/pip install firebase-admin
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- name: Execute Python Script Update
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env:
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CREDS_FILE: ${{ secrets.CREDS_FILE }}
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API_BASE_URL: ${{ secrets.API_BASE_URL }}
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run: |
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source venv/bin/activate
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if [[ "${{ github.event.inputs.type }}" == "overwrite" ]]; then
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python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) --overwrite
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else

‎.github/workflows/github-actions-update-rules.yml‎

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@@ -24,12 +24,14 @@ jobs:
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python-version: "3.10"
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- name: Install Python Packages
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run: |
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pip install firebase-admin
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python3 -m venv venv
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venv/bin/pip install firebase-admin
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- name: Execute Python Script Update
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env:
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CREDS_FILE: ${{ secrets.CREDS_FILE }}
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API_BASE_URL: ${{ secrets.API_BASE_URL }}
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run: |
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source ./venv/bin/activate
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echo ${{ github.event_name }}
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echo ${{ github.event.client_payload.type }}
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if [[ "${{ github.event_name }}" == "repository_dispatch" && "${{ github.event.client_payload.type }}" == "overwrite" ]]; then

‎.github/workflows/github-actions-yaml-test.yml‎

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@@ -23,9 +23,13 @@ jobs:
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- name: Check if FlowVariables.md is up to date
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run: |
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git diff --exit-code docs/user/FlowVariables.md
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- name: Install dependencies
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run: |
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python3 -m venv venv
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venv/bin/pip install --quiet yamlfix==1.17.0
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- name: Run yamlfix check
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run: |
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pip install --quiet yamlfix==1.17.0
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source venv/bin/activate
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yamlfix --version
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set -x
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yamlfix -c yamlfix.toml flow/scripts/variables.yaml

‎.gitignore‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@ flow/rc_model.bin
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flow/*.tif.gz
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flow/*.def.v
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# RePlAce deps
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*PORT9.dat
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*POST9.dat
@@ -103,3 +102,6 @@ bazel-bin
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bazel-out
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bazel-OpenROAD-flow-scripts
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bazel-testlogs
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# python venv
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venv/

‎flow/designs/asap7/aes-block/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set non_clock_inputs [all_inputs -no_clocks]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes-mbff/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
99

10-
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set non_clock_inputs [all_inputs -no_clocks]
1111

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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
99

10-
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
10+
set non_clock_inputs [all_inputs -no_clocks]
1111

1212
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes_lvt/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
99

10-
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
10+
set non_clock_inputs [all_inputs -no_clocks]
1111

1212
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/ethmac/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ set clk_period 1000
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set clk_io_pct 0.2
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set clk_port [get_ports $top_clk_name]
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create_clock -name $top_clk_name -period $clk_period $clk_port
6-
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
6+
set non_clock_inputs [all_inputs -no_clocks]
77
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
99

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